Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Prof. Dirk Timmermann, Claas Cornelius, Stephan Kubisch, Frank Sill, and Harald Widiger Course and contest Student: Enrico Daum

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design array of Carry Save Adders with last stage: Ripple Carry Adder 8 pipeline stages reminder goal Laouttool for standard cell design: Cadence FE Floorplanning Placement Routing

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design find a foorplan that will result in the smallest possible area while fullfilling all specifiations Depending on the interconnection (overhead) bunching cells that are part of a critical path (timing) power connection (area requirement). (clock tree to function) The problem is that it is not possible to determine whether or not it is possible to fullfill all requirements Floorplanning

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Currently power can only be distributed to the standard cells from the sides. Maybe for fast designs adding stripes improves the power distribution Powerplanning Placement & Routing too much space results in placements where the average distance between standard cells and consequently the delays caused by parasitics are larger !

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Floorplanning: Module Placer: Utilization 97.98% Powerplanning: add Vertical Stripe (improves the power distribution) Placement: add Filler Cells ( filler cells are used to fill any spaces between regular library cells to avoid planarity problems and provide electrical continuity for power and ground ) Optimization

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design results

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Problem with second layout Mul_top_setloads.scr contains some register/signals : set_load 0.00x mul_1/\carry9[7] Synopsys Result is: set_load 0.00x mul_1/\carry9[7] warning: cant find object mul_1/\carry9[7] error: design object list required… etc Therefore: comparisson to total dyn. powerdissipation is missing

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design conclusion & problems specific Cadence FE parameters didnt show effects at those little designs Few informations about parameters impact Conclusion: Changing the design!