Dr. H.v.d.Biggelaar / Mar3-Ver2 / 1 Engineering Technology Dr. H.v.d.Biggelaar March 22, 2000 State Machines in VHDL
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 2 State Machines Moore Mealy
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 3 similarities between the clocking of a bank of flip-flops and the flip-flops in a state machine
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 4 An example of an FSM used as a controller for two counters
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 5 case ps is when s0 => if x='1' then ns<=s0; else ns<=s1; end if; when s1 => if x='0 then ns<=s1; else ns<=s2; end if; when s2 => ns<=s0; when others => ns<=s0; end case;
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 6
7 Data Types Enumerated (user-defined): This is a list of values generated by the designer. Their synthesis is application-specific. The values of the elements in the list start at ‘0’ at the left “(“ and increment by one from there. Particularly useful in state machines. Example: type states is (idle, detect, send, receive); signal prsnt, next: states; Note: “Boolean” and “bit” are also enumerated types, defined by the IEEE standard. type Boolean is (false, true); type bit is (‘0’, ‘1’);
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 8 State machines Moore Machines A finite state machine in which the outputs change only due to a change of state Mealy Machines A finite state machine in which the outputs can change asynchronously i.e., an input can cause an output to change immediately
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 9 Moore state machine implementations (1) Outputs decoded from state bits Combinatorial decode Outputs are decoded combinatorially from the current state outputs comb = f(present state) Inputs Logic State Registers Output Logic Outputs
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 10 Moore state machine implementations (2) Outputs decoded from state bits Registered decode Outputs are registered; decode of outputs is in parallel with decode of next state outputs reg = f(previous state, inputs) Outputs State Registers Output Logic Output Registers Inputs Next State Logic Current State
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 11 StateOutput 1Output 2State Encoding s10000 s21001 s30110 Moore State Machine Implementations (3) Outputs encoded within state bits Example: Note: Both bits of the state encoding are used as outputs State Registers Outputs Inputs Logic
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 12 Complete code for a Moore machine with outputs q1 and q0 that reflect the value of the state variable.
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 13 Complete code for the same Moore machine as in the previous example, but with a single process.
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 14 One-Hot Encoding One state per flip-flop: in FPGA-type architectures reduces the next state logic requires fewer levels of logic cells enables high-speed state machines (> 100MHz). in CPLD-type architectures reduces the number of product terms can eliminate ‘expander’ product terms (i.e. reduce delays, and increase operating speed). but, uses more macrocells and there may not be enough Flip-Flops
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 15 Again the same Moore machine but this time with “one-hot” encoding Note that the values of the constants are chosen by the designer and thus are not limited to a “one-hot” sequence. For instance to minimize power, one may prefer a Gray code.
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 16 Mealy Machines Outputs may change with a change of state OR with a change of inputs. Mealy outputs are non-registered because they are functions of the present inputs Inputs State Registers Logic Outputs
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 17 ASM chart of a Mealy machine The only output “z” is ‘1’ when the machine is in state “s1” AND the input “x” is ‘1’.
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 18 Complete code for a Mealy machine with only a conditional output.
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 19 This simulation is not very useful. It does not show how “z” depends on the input “x” and the state.
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 20 The same Mealy machine but with output “q” added to show the value of the state variable.
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 21 This simulation is better. It’s clear now that “z” is a ‘1’ only when “x” is a ‘1’ AND the FSM is in state s1. However, the transitions of “x” take place only on the active edge of the clock, so you cannot tell if the response to the change in “x” is synchronous or asynchronous.
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 22 By just moving the transition of “x’ from coinciding with a leading edge of the clock to a level portion, it becomes obvious that when “x” goes from ‘1’ to ‘0’, the output “z” changes immediately, so that action is asynchronous.
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 23 Do you really want to do this?
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 24 reg ROM inputs outputs cen clock ROM-Centered Design top entity
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 25 pwait req ack ret reset clock q0_iq1_i d0_i d1_i ROM16x4 reg2 fsmrom a(0) a(1) a(2) a(3) d(0) d(1) d(2) d(3) clk rst q1 q0 d1 d0 ROM-Centered Design
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 26 Example: for addr = 0, the data is “0110” (B-A-ret-ack) or 6 (hex)
Dr. H.v.d.Biggelaar / Mar3-Ver2 / 27 And that’s IT for State Machines And that’s IT for State Machines