GA-M59SLI-S5 introduction
nForce 500 Series Chipset nForce 500 Series nForce 590 SLI nForce 570 Ultra nForce 550 Features Segment Enthusiast SLI (2x16) Performance SLI SLI (2x8) Performance non-SLI Mainstream CPU Athlon 64 FX Athlon 64 X2 Athlon 64 Athlon 64 FX Athlon 64 X2 Sempron NVIDIA LinkBoost™ technology Yes No NVIDIA® SLI™ Technology 2 x 16 1 x16, 2 x 8 PCI Express Lanes 46 lanes 28 lanes 20 lanes PCI Express Links 9 links 6 links 5 links Configuration 16, 16, 8, 1, 1, 1,1, 1, 1 16, 8, 1, 1, 1,1 16, 1, 1, 1,1 SATA/PATA drives 6 SATA 2 PATA 4 SATA 2 PATA SATA speed 3Gb/s RAID 0,1,0+1,5 0,1,0+1 Native Ethernet Connection 2 x 10/100/1000 1 x 10/100/1000 NVIDIA FirstPacket™ technology NVIDIA DualNet® technology Teaming TCP/IP Acceleration NVIDIA nTune™ Utility USB ports 10 PCI Slots 5 Audio HDA Date:2017/4/21
nForce 550 Block Diagram Date:2017/4/21
nForce 570 Ultra Block Diagram Date:2017/4/21
nForce 570 SLI Block Diagram Date:2017/4/21
nForce 590 Block Diagram Date:2017/4/21
MCP55PXE Diagram Internal Bus Hyper Transport Link Date:2017/4/21 The NVIDIA MCP55PXE integrates the following features 1 GHz HyperTransport x16 up and down links to the AMD Socket AM2 CPUs Six separate and independent PCI Express controllers and twenty eight PCI Express lanes Three separate SATA controllers, each with integrated dual PHYs that are capable of operating at 1.5 Gbps and 3.0 Gbps speeds Fast ATA-133 IDE controller Support for a master device and a slave device NVIDIA MediaShield™ RAID with support for RAID 0, RAID 1, RAID 0+1, RAID 5, and JBOD Dual IEEE 802.3 NVIDIA MACs for 1000BASE-T/100BASE-T/10BASE-T Gigabit/Fast Ethernet/Ethernet with TCP Offload Engine (TOE) RGMII for Gigabit/Fast Ethernet/Ethernet OR MII for Fast Ethernet/Ethernet IPMI 2.0 pass through support for remote management Integrated management processor with dedicated SMBUS and dedicated GPIOs USB 2.0 EHCI and USB 1.1 OHCI Supports up to ten ports PCI 2.3 interface Supports up to 5 PCI slots with dedicated REQ/GNT pairs Dual SMBus 2.0 interfaces UAA (Universal Audio Architecture) High Definition Audio interface Supports up to 3 external UAA High Definition Audio codecs for 7.1 channel audio Supports 32-bit / 192 kHz audio functionality LPC bus 1.0 compatible interface Integrated AT legacy controllers Integrated clock synthesizer with spread spectrum capability Programmable active power management unit Integrated serial port AMD Socket AM2 CPUs power sequencing protection logic 33 mm × 33 mm, 1 mm ball pitch, PBGA Management Processor Legacy SATA 3 Gb/s Serial ATA 3 Gb/ s PCI Express Serial ATA 3 Gb/ s Serial ATA 3 Gb/ s 2 Drives PCI-33 10 Ports Internal Bus LPC BUS RGMII/MII RGMII SMBus HDA RS232 Hyper Transport Interface Hyper Transport Link NVIDIA SPP Date:2017/4/21
Hyper Transport Link @ 1 GHz Hyper Transport Link @ 1 GHz C51XE Diagram The NVIDIA C51XE includes the following features: Primary HyperTransport link, up to 1.0 GHz to the CPU Secondary HyperTransport link, up to 1.0 GHz PCI Express 16 lane link interface for external graphics processors Dual PCI Express single lane link interface, with dedicated controller for other peripherals Integrated power management processor Programmable clock synthesizer 25 mm × 25 mm, 1.0 mm ball pitch PBGA MCP51XE Hyper Transport Link @ 1 GHz Hyper Transport Interface x1 External PCI Express Device PCI Express x1 Root Port Internal Bus x1 PCI Express x1 Root Port External PCI Express Device x16 PCI Express x16 Root Port External PCI Express Device Active Power Management Integrated Clock Synthesizer Hyper Transport Interface Hyper Transport Link @ 1 GHz AMD Athlon 64/Athlon 64 FX Processors Date:2017/4/21
GA-M59SLI-S5 BLOCK DIAGRAM Date:2017/4/21
Power On Off Circuitry nVIDIA MCP55P IT8716 5VSB→5VDUAL 25.00MHZ 32.768KHZ 3VDUAL 3VDUAL RTCVDD -RTCRST BATTERY nVIDIA MCP55P VBAT VCC12DUAL PWRBTSW SLP_S3 5VSB System On-Off Button PSIN SB_PWOK -PWRBTSW ATX Power Supply -IO_PSON PS ON# IT8716 Date:2017/4/21
System Reset Map C51XE MCP55P AMD K8 AM2 PCIE_1 PCIE_16_1 PCIE_2 PCIE_RST# HT_CPU_PWRGD PCIE_1 AMD K8 AM2 C51XE PCIE_16_1 HT_CPU_RST# PCIE_2 HTMCP_PWRGD PCIE_8 HTMCP_RST# PCIE_16_2 ATX SLP_S3# PS ON PWRGD PCI SLOT PWOK PPCIRST#_SLOT1 MCP55P PPCIRST#_SLOT2 ALC888 ACZ_RST# IDERST# 1394RST# LPCRST_SIO# LPCRST_FLASH# MII_RST# IDE SB_PWOK DUAL BIOS IEEE 1394 TSB43AB23 MARVELL 88E1116 MARVELL 88E1116 ITE 8716GB/CX Date:2017/4/21
C51XE/MCP55PXE Power Sequencing Block Diagram AMD K8 AM2 HT_CPU_PWRGD HT_CPU_RST# HT_CPU_UP HT_CPU_DN CPU_CLK PRSNT# PERST# C51XE PE_REFCLK# HT_MCP_PWRGD HT_MCP_RST# HT_STOP# HT_MCP_UP HT_MCP_DN CR_REF_CLK HT_REQ# PCIRST# HT_VLD HT_VDD_EN MCP55P CPU_VLD CPU_VDD_EN MEM_VLD SLP_S3# CK8_PWOK SLP_S5# SB_PWOK LPC_PD# ROM Date:2017/4/21
GA-M59SLI-S5 System Clock HT_CPU_TX_CLK[0:1]_N HT_CPU_RX_CLK[0:1]_P CLKOUT 200MHZ_N CLKIN 200MHZ_P HT_CPU_RX_CLK[0:1]_N CLKOUT 200MHZ_P CLKIN 200MHZ_N HT_CPU_TX_CLK[0:1]_P HT_MCP_TX_CLK[0:1]_P HT_MCP_TX_CLK[0:1]_N HT_MCP_RX_CLK[0:1]_P HT_MCP_RX_CLK[0:1]_N CLKIN_25MHZ CLKOUT_25MHZ LPC_CLK1 HDA_BCLK MA0_CLK[2:0]_N MB0_CLK[2:0]_N MA1_CLK[2:0]_N MA1_CLK[2:0]_P MA0_CLK[2:0]_P MB0_CLK[2:0]_P MB1_CLK[2:0]_P MB1_CLK[2:0]_N DIMM 0 MEM_B0 DIMM 0 MEM_B1 DIMM 0 MEM_A0 DIMM 0 MEM_A1 BUF_SIO_CLK LPC_CLK0 PCI_CLK0 PCI_CLK3 PCI_CLK2 PCI_CLK1 PCI_CLK4 PCI_CLKIN PCI_CLK5 PE0_REFCLK_N PE0_REFCLK_P PEX X 16 PE1_REFCLK_N PE2_REFCLK_N PE2_REFCLK_P PE1_REFCLK_P PEX X 8 PE5_REFCLK_N PE5_REFCLK_P PEX X 1 PE3_REFCLK_P PE3_REFCLK_N GIGABYTE SATA 2 Super I/O PCICLK1 PCICLK2 TPM 1394CLK BIOS HDA CODEC XTALIN XTALOUT XTALIN_RTC XTALOUT_RTC Date:2017/4/21
Power-Up Sequence *Core Planes include: +1.2V Core, +1.5V_PLL_HT, +3.3V_PLL_HT, +1.5V_PE_PLL_AVDD, +1.5V_PE_PLL_DVDD, +1.5V_PE_PLL_CORE +1.5V_PE_D, +1.5V_PE_A, +3.3V_PE_PLL_CORE, +1.5V_SP_PLL_AVDD, +1.5V_SP_PLL_DVDD, +1.5V_SP_PLL_CORE +1.5V_SP_D, +1.5V_SP_A, +3.3V_SP_PLL_CORE, +3.3V_PLL_CPU, +3.3V_PLL_USB +3.3V, +5.0V_CLAMP Date:2017/4/21
AMD Socket 939 Architecture Date:2017/4/21
AMD Socket 940 Architecture Date:2017/4/21
CPU HYPER TRANSPORT INTERFACE Date:2017/4/21
Hyper Transport Link Interconnect HT_RXCAD[15:8]_P HT_RXCAD[15:8]_L HT_RXCLK1_P HT_RXCLK1_N VCC12_HT HT_TXCTL_P HT_TXCTL_N HT_TXCAD[7:0]_P HT_TXCAD[7:0]_L HT_TXCLK0_P HT_TXCLK0_L HT_TXCAD[15:8]_P HT_TXCAD[15:8]_L HT_TXCLK1_P HT_TXCLK1_L HT_RXCTL_P HT_RXCTL_N CTLOUT0_H CTLOUT0_L HT_RXCAD[7:0]_P HT_RXCAD[7:0]_L HT_RXCLK0_P HT_RXCLK0_L CADOUT(7:0)_H CADOUT(7:0)_L CLKOUT0_H CLKOUT0_L CTLOUT1_H CTLOUT1_L CADOUT(15:8)_H CADOUT(15:8)_L CLKOUT1_H CLKOUT1_L CTLIN0_H CTLIN0_L CADIN(7:0)_H CADIN(7:0)_L CLKIN0_H CLKIN0_L CADIN(15:8)_H CADIN(15:8)_L CLKIN1_H CLKIN1_L AMD CPU GND LDTRST_L (-CPURST) PWROK (CPU_PWRGD) LDTSTOP_L (HTSTOP_L) Date:2017/4/21
Memory Interface Channel A Date:2017/4/21
Memory Interface Channel B Date:2017/4/21
DDR2 SDRAM Memory Interface Pin Descriptions Signal Name Type Description M[B, A][1:0]_CLK_H/L[2:0] O-IOD DRAM Differential Clock M[B, A][1:0]_CS_L[1:0] O-IOS DRAM Chip Selects M[B, A][1:0]_ODT[0] DRAM Enable Pin for On Die Termination M[B, A]_CKE[1:0] DRAM Clock Enable M[B, A]_DQS_H/L[8:0] B-IOD DRAM Differential Data Strobe M[B, A]_DATA[63:0] B-IOS DRAM Interface Data Bus M[B, A]_DM[8:0] DRAM Data Mask Bits M[B, A]_CHECK[7:0] DRAM Interface ECC Check Bits M[B, A]_RAS_L DRAM Row Address Select M[B, A]_CAS_L DRAM Column Address Select M[B, A]_WE_L DRAM Write Enable M[B, A]_ADD[15:0] DRAM Column/Row Address M[B, A]_BANK[2:0] DRAM Bank Address M_VREF VREF DRAM Interface Voltage Reference M_ZP A Compensation Resistor tied to VSS M_ZN Compensation Resistor tied to VDDIO Date:2017/4/21
Unbuffered 4-DIMM Block Diagram MB1_CLK_H[2:0], MB1_CLK_L[2:0] MA1_CLK_H[2:0], MA1_CLK_L[2:0] MB0_CLK_H[2:0], MB0_CLK_L[2:0] MA0_CLK_H[2:0], MA0_CLK_L[2:0] MA_ADD[15:0], MA_BANK[2:0] MB_ADD[15:0], MB_BANK[2:0] MA_RAS_L,MA_CAS_L,MA_WE_L MB_RAS_L,MB_CAS_L,MB_WE_L MA0_CS_L[1:0],MA_CKE[0],MA0_ODT[0] MA1_CS_L[1:0],MA_CKE[1],MA1_ODT[0] MB1_CS_L[1:0],MB_CKE[1],MB1_ODT[0] MB0_CS_L[1:0],MB_CKE[0],MB0_ODT[0] MB_DATA[63:0],MB_CHECK[7:0] MA_DATA[63:0],MA_CHECK[7:0] MA_DQS_H[8:0],MA_DQS_L[8:0] MB_DQS_H[8:0],MB_DQS_L[8:0] MB_DM[8:0] MA_DM[8:0] Unbuffered DDR2 SDRAM 240 DIMM DIMM A0 DIMM A1 DIMM B0 DIMM B1 AM2 Socket Processor Date:2017/4/21
Power-Up Signal Sequencing Date:2017/4/21
CPU VCORE Date:2017/4/21
MCP55XE Power Signal Description Date:2017/4/21 +3.3V_VBAT 3.3 V Battery Voltage (2.0V~3.45V) This voltage powers the RTC. +3.3V_DUAL 3.3 V Sleep Mode Power This voltage powers the power management interface to 3.3 V peripherals. +3.3V_USB_DUAL 3.3 V USB Power (connect to 3VDual) This voltage powers the integrated USB controllers. Connect this signal directly on the motherboard to the +3.3 V_DUAL power plane. +3.3V_PLL_MAC_DUAL 3.3 V MAC PLL Standby Power (connect to 3VDual) This voltage powers the MAC PLL during power management states. +1.2V_DUAL 1.2 V Sleep Mode Core Power This voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5. +5V 5 V Power This voltage is used as the reference voltage for the 5 V tolerant I/O. +3.3V 3.3 V Power This voltage powers the 3.3 V interface to 3.3 V peripherals. +3.3V_HT 3.3 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry. +3.3V_PLL_CPU 3.3 V CPU Interface PLL Power (connect to VCC3) This voltage powers the PLL of the CPU interface. +3.3V_PLL_HT 3.3 V HyperTransport PLL Power (connect to VCC3) This voltage powers the PLL of the HyperTransport interface. +3.3V_PLL_USB 3.3V USB PLL Power (connect to VCC3) This voltage powers the USB PLL. +3.3V_PLL_PE_SS 3.3 V PCI Express Spread Spectrum PLL Power (connect to VCC3) This voltage powers the spread spectrum PLL of the PCI Express interface. +3.3V_PLL_SP_SS 3.3 V SATA Spread Spectrum PLL Power (connect to VCC3) This voltage powers the spread spectrum PLL of the SATA interface. Date:2017/4/21
MCP55XE Power (Cont) Date:2017/4/21 Signal Description +1.5V 1.5 V Core Power This voltage powers the core of the NVIDIA MCP55PXE. +1.5V_PEA 1.5 V PCI Express Analog Power (connect to VCC1.5) This voltage powers the analog section of the PCI Express interface. +1.5V_PLL_CPU_HT 1.5 V HyperTransport PLL Power (connect to VCC1.5) This voltage powers the HyperTransport PLL clock drivers. +1.5V_PLL_PE_SS 1.5 V PCI Express Spread Spectrum PLL Power (connect to VCC1.5) This voltage powers the spread spectrum PLL of the PCI Express interface. +1.5V_PLL_PE 1.5 V PCI Express PLL Power (connect to VCC1.5) This voltage power the PLL of the PCI Express interface. +1.5V_PLL_SP_SS 1.5 V SATA Spread Spectrum PLL Power (connect to VCC1.5) This voltage powers the spread spectrum PLL of the SATA interface. +1.5V_PLL_SP_VDD 1.5 V SATA PLL Power (connect to VCC1.5) This voltage powers the PLL of the SATA interface. +1.5V_PLL_USB 1.5 V USB PLL Power (connect to VCC1.5) This voltage powers the PLL of the USB interface. +1.5V_SP_A 1.5 V SATA Analog Power (connect to VCC1.5) This voltage powers the analog section of the integrated SATA. +1.5V_SP_D 1.5 V SATA Digital Power (connect to VCC1.5) This voltage powers the digital section of the integrated SATA. +1.2V 1.2 V Core Power (connect to VCC1.5) +1.2V_HT 1.2 V HyperTransport Power This voltage powers the HyperTransport interface. GND Ground Date:2017/4/21
RTCVDD VCC12_HTMCP VCC12DUAL VCC15V 3VDUAL VCC3 Date:2017/4/21 +3.3V +3.3V_HT +3.3V_PLL_CPU +3.3V_PLL_HT +3.3V_PLL_USB +3.3V_PLL_PE_SS +3.3V_PLL_SP_SS +1.5V +1.5V_PEA +1.5V_PLL_CPU_HT +1.5V_PLL_PE_SS +1.5V_PLL_PE +1.5V_PLL_SP_SS +1.5V_PLL_SP_VDD +1.5V_PLL_USB +1.5V_SP_A +1.5V_SP_D +1.2V +1.2V_HT +3.3V_VBAT +3.3V_DUAL +3.3V_USB_DUAL +3.3V_PLL_MAC_DUAL +1.2V_DUAL +5V VCC12_HTMCP VCC15V 3VDUAL RTCVDD VCC3 VCC12DUAL Date:2017/4/21
C51XE Power Description Signal Description Date:2017/4/21 +1.2V_CORE Core Power Rail This voltage powers the core logic of the C51XE. It is derived from the main silver box “PS_ON” power supply rails. +1.2V_HT Isolated HyperTransport Power Rail Since the +1.2V_CORE power rail is enabled simultaneously with the +3.3V main power supply rail and before the CPU power is valid, the enable of this rail must be delayed to honor the AMD power sequence. Most NVIDIA MCP devices have timed digital sequencer outputs. These can be used to accurately control this sequence in accordance with AMD regulations and without using highly variable RC timing circuits. +1.2V_HTMCP HyperTransport to MCP Power Rail This voltage powers the HyperTranport interface between the C51XE and the MCP51. +1.2V_PEA +1.2V PCI Express Analog Voltage This is a filtered version of the +1.2V_CORE power supply and is used to power the analog circuits of the PCI Express block. +1.2V_PED +1.2V PCI Express Digital Voltage power the digital circuits of the PCI Express block. +1.2V_PLL +1.2V PLL Voltage power some of the internal PLLs. +1.2V_PLLCORE +1.2V Core PLL Voltage This voltage powers the PLL of the core logic. It is a filtered version of the +1.2V_CORE voltage. +1.2V_PLLHTCPU +1.2V CPU HT PLL Voltage This voltage powers the PLL of the HyperTransport interface to the CPU. It is a filtered version of the +1.2V_CORE voltage. +1.2V_PLLHTMCP +1.2V MCP HT PLL Voltage This voltage powers the PLL of the HyperTransport interface to the MCP. It is a Date:2017/4/21
C51XE Power Description (cont) Signal Description +1.2V_PLLIFP +1.2V Voltage This voltages rails is not used by C51XE. It should be pulled down to GND through a 4.7 kΩ resistor. +1.2V_PLLGPU This voltages rails is not used by C51XE. It should be pulled down to GND through a 4.7 kΩ resistor. +2.5V_CORE 2.5V Core Voltage This voltage is used to power the core logic of the C51XE. It is derived from the main silver box “PS_ON” power supply rails. +2.5V_PLLCORE +2.5V Core PLL Voltage This voltage powers the core PLL. It is a filtered version of the +2.5V_CORE voltage. +2.5V_PLLGPU +2.5V GPU PLL Voltage +2.5V_PLLHTCPU +2.5V CPU HT PLL Voltage This voltage powers the PLL of the HyperTransport interface to the CPU. It is a filtered version of the +2.5V_CORE voltage. +2.5V_PLLIFP +2.5V IFP PLL Voltage +3.3V +3.3V Voltage This voltage is the +3.3V rail supplied by the main silver box power supply. It is used to power the +3.3V I/Os. +3.3V_DAC +3.3V DAC Voltage This voltage power the video output DAC. It is a filtered version of the +3.3V power supply. +2.5V_IFPA +2.5V Voltage This voltage rail is not used by C51XE. It should be pulled down to GND through a 4.7 kΩ resistor. +2.5V_IFPB Date:2017/4/21
C51XE POWER Date:2017/4/21
5VSB 5VDUAL Date:2017/4/21
5VDUAL3VDUAL Date:2017/4/21
3VDUALVCC12DUAL Date:2017/4/21
DDRV18V Date:2017/4/21
S5_EN Date:2017/4/21
DDRVTT Date:2017/4/21
VCC15 Date:2017/4/21
VCC12 Date:2017/4/21
VCC12_HT Date:2017/4/21
VCC12_HTMCP Date:2017/4/21
VDDA25 Date:2017/4/21
VCC2P5V_PWR Date:2017/4/21
CK8_ PWOK Date:2017/4/21
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