High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/ Semester Project Date: Januar 2010 Part B - Final Presentation

Project Goal Designing a SpaceWire Switch Core (Router) compatible to ECSS-E-50-12A standard with the “Path Addressing” routing scheme. Project Results D1117_SPWPort – SpaceWire Network Device D1117_SPWRepeater – SpaceWire Network Repeater D1117_SPWRouter – SpaceWire Router D1117_SPWPort – SpaceWire Network Device D1117_SPWRepeater – SpaceWire Network Repeater D1117_SPWRouter – SpaceWire Router

System Topology SpaceWire Router

System Topology D1117_SPWRouter PORT Low latency Point-to-point Wormhole Routing Asynchronous communication Path Addressing 100 Mb/s of Total Traffic.

Layer 2 (Character Level) Network Port Receiver D1117 SpaceWire Port Architecture Port Controller Din Sin Dout Sout Sys Clock Reset RX DATA / Control TX DATA / Control Link Start State Machine Transmitter FIFO RX CLOCK FIFO Write Ready Read Ready Write Link Ready Tx Clock

System Topology D1117_SPWRouter PORT Low latency Point-to-point Wormhole Routing Asynchronous communication Path Addressing 100 Mb/s of Total Traffic.

SpaceWire Packet Format SpaceWire Packet A SpaceWire ‘Routing Switch’ shall transfer packets from the input port of the switch where the packet arrives, to a particular output port determined by the packet destination address. SpaceWire ‘Routing Switch’

Routing with Path-Addressing Cargo EOP

Layer 2 Repeater SPW Port-0 Read Interface RX_EMPTY READ_EN RX_CONTROL RX_DATA SPW Port-1 Write Interface TX_FULL TX_WRITE TX_CONTROL TX_DATA SpaceWire Connection Broker SpaceWire signals D1117_SPWRepeater ENABLE

Router Architecture Read Interface Read Interface SpaceWire Mux SPW Port-0 Read Interface RX_EMPTY READ_EN RX_CONTROL RX_DATA SPW Port-1 Read Interface RX_EMPTY READ_EN RX_CONTROL RX_DATA SPW Port-2 Read Interface RX_EMPTY READ_EN RX_CONTROL RX_DATA SPW Port-0 Write Interface TX_FULL TX_WRITE TX_CONTROL TX_DATA SPW Port-1 Write Interface TX_FULL TX_WRITE TX_CONTROL TX_DATA SPW Port-2 Write Interface TX_FULL TX_WRITE TX_CONTROL TX_DATA Write Interface Write Interface SpaceWire Mux RX_EMPTY READ_EN RX_CONTROL RX_DATA TX_FULL TX_WRITE` TX_CONTROL TX_DATA SpaceWire Connection Broker Source Address Register SpaceWire Router Control HEADER_DELETION EN_DEST_ADDR_REGISTER REGISTERED_SOURCE_ADDR Packet Detection Unit Destination Address Register REGISTERED_DEST_ADDR SYSTEM_CLOCK EN_SOURCE_ADDR_REGISTER EOP Detection Unit EN_PACKET_DELIVERY PACKET_DETECTEDEOP_DETECTED

Router Controller

Hardware in test GR-RASTA running D1117_SPWRouter as SpaceWire router. Gaisler GRESB – Gaisler Ethernet Bridge. (To be explained.) 3 PCs as SpacWire stations connected to one D1117 SpaceWire Router. Together they form a SpaceWire network based on ‘Path Addressing’ routing. GR-RASTA running D1117_SPWRouter as SpaceWire router. Gaisler GRESB – Gaisler Ethernet Bridge. (To be explained.) 3 PCs as SpacWire stations connected to one D1117 SpaceWire Router. Together they form a SpaceWire network based on ‘Path Addressing’ routing.

Software in test TCP Test Tool 2.3 Freeware.

Main Test Topology Core: D1117 SpaceWire Router FPGA: GR-RASTA SPW-0SPW-1SPW-2 Logic Link PC-0 OS: Windows PC-1 OS: Windows PC-2 OS: Windows

Main Test Topology Core: D1117 SpaceWire Router FPGA: GR-RASTA SPW-0SPW-1SPW-2 PC-0 OS: Windows PC-1 OS: Windows PC-2 OS: Windows Gaisler SpaceWire Ethernet Bridge Ethernet SpaceWire

SpaceWire Ethernet Bridge Gaisler SpaceWire Ethernet Bridge Ethernet SPW Physical Port Ethernet/IPv4/TCP - Transmit Ethernet/IPv4/TCP - Receive #0SPW #1SPW #2SPW

Main Test Topology Core: D1117 SpaceWire Router FPGA: GR-RASTA SPW-0SPW-1SPW-2 PC-0 OS: Windows PC-1 OS: Windows PC-2 OS: Windows Gaisler SpaceWire Ethernet Bridge Ethernet SpaceWire

PC-0 Path Address Destination Address Cargo TCP Message Header specifying transmission of a SpaceWire packet the size of 6 bytes. IP Address of GRESB on the IP network. The TCP Listening Socket on the GRESB TCP port corresponds for transmission on SpaceWire port 0. Send button for dispatching the TCP Message to GRESB

Main Test Topology Core: D1117 SpaceWire Router FPGA: GR-RASTA SPW-0SPW-1SPW-2 PC-0 OS: Windows PC-1 OS: Windows PC-2 OS: Windows Gaisler SpaceWire Ethernet Bridge Ethernet SpaceWire

PC-1 Encapsulated SpaceWire Packet TCP Message Header specifying reception of a SpaceWire packet the size of 5 bytes.

Test Miscellaneous “2 Routers Topology” was tested in addition to the “Main Topology” to simulate complex routes in a SpaceWire network with more then one router. D1117_SPWRouter delivered successfully thousands of SpaceWire packets originated in PCs, to correct destinations which are PCs as well on the same SpaceWire network. “2 Routers Topology” was tested in addition to the “Main Topology” to simulate complex routes in a SpaceWire network with more then one router. D1117_SPWRouter delivered successfully thousands of SpaceWire packets originated in PCs, to correct destinations which are PCs as well on the same SpaceWire network.

Further Possibilities The router can be redesigned for multiple connections ‘routing matrix’. Currently the datapath of the router can only support one simultaneous connection from port to port. The router can be extended to support more SpaceWire routing schemes. (Not just Path Addressing + Header Deletion). The router can be redesigned for higher data rate ~200Mhz on the XC2v6000 FPGA using pipeline design. Writing a software Device Driver for windows to virtually make GRESB a SpaceWire network connection on a PC. It can be done by implementing a Device Driver which exposes an Ethernet Device abstraction towards Windows and on the other side, coding SpaceWire packets on GRESB. Such a Device Driver actually solves the problem of “Ethernet over SpaceWire” for PC. The router can be redesigned for multiple connections ‘routing matrix’. Currently the datapath of the router can only support one simultaneous connection from port to port. The router can be extended to support more SpaceWire routing schemes. (Not just Path Addressing + Header Deletion). The router can be redesigned for higher data rate ~200Mhz on the XC2v6000 FPGA using pipeline design. Writing a software Device Driver for windows to virtually make GRESB a SpaceWire network connection on a PC. It can be done by implementing a Device Driver which exposes an Ethernet Device abstraction towards Windows and on the other side, coding SpaceWire packets on GRESB. Such a Device Driver actually solves the problem of “Ethernet over SpaceWire” for PC.

End