1 Hardware synthesis 2.0 Byron Cook and Satnam Singh with Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiri Simsa, and Viktor Vafeiadis TexPoint fonts used in EMF. Read the TexPoint manual before you delete this box.: A A A

2 Explosion of advances in program verification Impossible 10 years ago, standard today  SLAM, SpaceInvader, ARMC, Thor, RGSep, TERMINATOR, etc  WP synthesis, WLP synthesis, Challenges in automatic program verification  Concurrency  Data structures  Scalability/precision  Productization  New applications

3 Beyond proving correctness Can we use these techniques elsewhere?  Compilers ?  Operating systems?  Language runtimes? Current focus: hardware synthesis  Synthesis for heap-based programs using techniques from termination provers  Automatically parallelize circuits, and localize memories on chip using techniques from heap analysis  Aggressive unrolling of loops during synthesis using complexity analysis

Can we use these tools elsewhere?  Compilers ?  Operating systems?  Language runtimes? Current focus: hardware synthesis  Synthesis for heap-based programs using techniques from termination provers  Automatically parallelize circuits, and localize memories on chip using techniques from heap analysis  Aggressive unrolling of loops during synthesis using complexity analysis 4 Beyond proving correctness

Can we use these tools elsewhere?  Compilers ?  Operating systems?  Language runtimes? Current focus: hardware synthesis  Synthesis for heap-based programs using techniques from termination provers  Automatically parallelize circuits, and localize memories on chip using techniques from heap analysis  Aggressive unrolling of loops during synthesis using complexity analysis 5 Beyond proving correctness

Can we use these tools elsewhere?  Compilers ?  Operating systems?  Language runtimes? Current focus: hardware synthesis  Synthesis for heap-based programs using techniques from termination provers  Automatically parallelize circuits, and localize memories on chip using techniques from heap analysis  Aggressive unrolling of loops during synthesis using complexity analysis 6 Beyond proving correctness

Can we use these techniques elsewhere?  Compilers ?  Operating systems?  Language runtimes? Current focus: hardware synthesis  Synthesis for heap-based programs using techniques from termination provers  Automatically parallelize circuits, and localize memories on chip using techniques from heap analysis  Aggressive unrolling of loops during synthesis using complexity analysis 7 Beyond proving correctness

8 Hardware synthesis C file Hardware Synthesis

9 Hardware synthesis C file Hardware Synthesis

10 Hardware synthesis C file Hardware Synthesis

11 Hardware synthesis C file Hardware Synthesis

12 Hardware synthesis Hardware Synthesis

13 Hardware synthesis Hardware Synthesis

14 Hardware synthesis Hardware Synthesis

15 Hardware synthesis C file Shape Analysis α file pass Termination Analysis error pass X X error X X Bounds Synthesis X X failure Hardware Synthesis

16 Hardware synthesis C file

17 Hardware synthesis C file Shape Analysis α file pass error X X

18 Hardware synthesis C file Shape Analysis α file pass error X X

19 Hardware synthesis X X

20 Hardware synthesis C file Shape Analysis α file pass Termination Analysis error pass X X error X X

21 Hardware synthesis C file Shape Analysis α file pass Termination Analysis error pass X X error X X Bounds Synthesis X X failure pass

22 Hardware synthesis C file Shape Analysis α file pass Termination Analysis error pass X X error X X Bounds Synthesis X X failure pass

23 Hardware synthesis C file Shape Analysis α file pass Termination Analysis error pass X X error X X Bounds Synthesis X X failure pass

24 Hardware synthesis C file Shape Analysis α file pass Termination Analysis error pass X X error X X Bounds Synthesis X X failure pass

25 Hardware synthesis C file Shape Analysis α file pass Termination Analysis error pass X X error X X Bounds Synthesis X X failure pass

26 Hardware synthesis C file Shape Analysis α file pass Termination Analysis error pass X X error X X Bounds Synthesis X X failure pass

27 Hardware synthesis C file Shape Analysis α file pass Termination Analysis error pass X X error X X Bounds Synthesis X X failure pass

28 Hardware synthesis C file Shape Analysis α file pass Termination Analysis error pass X X error X X Bounds Synthesis X X failure Hardware Synthesis

29 Hardware synthesis C file Shape Analysis α file pass Termination Analysis error pass X X error X X Bounds Synthesis X X failure Hardware Synthesis

30 Hardware synthesis pass error pass X X error X X X X failure α file Shape Analysis Termination Analysis Bounds Synthesis Hardware Synthesis C file

31 α file failure Hardware synthesis Shape Analysis pass Termination Analysis error pass error Bounds Synthesis X X X X C file Precondition Synthesis X X

32 α file failure Hardware synthesis Shape Analysis pass Termination Analysis error pass error Bounds Synthesis X X X X C file Precondition Synthesis X X

Altera DE2 FPGA Board 33

Altera synthesis/implementation tools 34

Synthesized logic 35

VHDL simulation of prio netlist 36

Logic analyzer output 37

38 Conclusion Big advances in formal verification, analysis, understanding Alternative uses for these new techniques?  Compiling for embedded systems or hardware?  Automatic parallelization?  Speculative execution and rollback?  Mixed static/dynamic property checking in runtimes?  Runtime verification of progress (i.e. termination)? Current project  Solving open problems in hardware synthesis  Further blurring the line between hardware and software  Demo: first-known synthesis tool supporting dynamic heap

39 Conclusion Big advances in formal verification, analysis, understanding Alternative uses for these new techniques?  Compiling for embedded systems or hardware?  Automatic parallelization?  Speculative execution and rollback?  Mixed static/dynamic property checking in runtimes?  Runtime verification of progress (i.e. termination)? Current project  Solving open problems in hardware synthesis  Further blurring the line between hardware and software  Demo: first-known synthesis tool supporting dynamic heap