1. EECS 249 Dec 4, 1999 Extending POLIS with User Defined Data Types Arvind Thirunarayanan Extending POLIS with User Defined Data Types Arvind Thirunarayanan

2. Overview What is POLIS? Design Flow Project Description Proposed Solution Current/Future Work

3. What is POLIS? System Design –initially HW/SW –function architecture co-design Co-design environment –mixed system –specification, synthesis, estimation, verification Embedded system

4. Design Flow - Simulation Path Initial specification of embedded system –high level language - Esterel –compile into SHIFT Read into POLIS –create/ optimize internal graph representation –generate C/Ptolemy code for each module Functional/Performance simulation –validation to analyze performance –repartition to evaluate implementation

5. Design Flow - Synthesis Path Read into POLIS –partition each module into hardware/software –Hardware Translate into a hardware format like VHDL,BLIF Optimize and write netlist –Software create/ optimize internal graph representation generate RTOS and C code for each module Generate hardware and software implementation

6. Project Description Motivation –Two Chip Intercom (TCI) Project at BWRC Current POLIS –no support for user-defined data types –use of events data of integer types only –workaround for floats Project implementation –change SHIFT to include user-defined types –extend the changes through the synthesis paths

7. Aux file –type definitions –structs, arrays SHIFT file –not just a bit –add type information Synthesis path –translate to synthesized types –VHDL records Proposed Solution Esterel Auxiliary file SHIFT HWSW

8. File.aux typedef struct { int re; int im; } cplx; typedef array arr_name int 20; Aux file –type definitions –structs, arrays SHIFT file –not just a bit –add type information Synthesis path –translate to synthesized types –VHDL records Proposed Solution

9. Aux file –type definitions –structs, arrays SHIFT file –not just a bit –add type information Synthesis path –translate to synthesized types –VHDL records Proposed Solution File.shift.net net_sender.inputs *i1.outputs *o1(o1).nb o1 0 ….end

10. File.shift.net net_sender.type int 16.type struct cplx re im.dt re int.dt im int.inputs *i1.outputs *o1(o1).dt o1 cplx ….end Aux file –type definitions –structs, arrays SHIFT file –not just a bit –add type information Synthesis path –translate to synthesized types –VHDL records Proposed Solution

11. Current/Future Work Current changes in tool implementation in SHIFT  code for automatic generation SHIFT from user input  manual definition of translation synthesis from SHIFT Future work –generate type declaration for synthesis currently done by hand –functions to access the data types