Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design d Meeting Spezielle Anwendungen des VLSI – Entwurfs Special applications of VLSI design 3 rd Meeting (intermediate meeting) Prof. Dirk Timmermann, Frank Sill, Ronald Hecht, Stephan Kubisch, Harald Widiger, Claas Cornelius Course and contest

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Agenda 1.Presentation of results after first steps with Synopsys Design Analyzer: 1.Results for delay, power (CE-group) 2.Results for speed, power, area (ET/ITTI – group) 2.Hints for further optimizations

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Results for delay / power (CE - group) max. 5 minutes 1.Kwang Yoal Kim 2.Victor Luyali 3.Vinod Kumar Kothapalli 4.Predrag Jankovic (no slides) 5.Amit Hingher 6.Jiaxi You (ill)

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Results for speed, power, area (ET/ITTI) max. 5 minutes 1.Jens Schulz / Petra Bravermann 2.Andreas Tockhorn / Hagen Sämrow 3.Martin Siemroth / Mathias Rulf 4.Markus Hempel / Tim Eickelberg 5.Peter Danielis / Peter Kröger

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Hints for further optimizations Read the manual! From Unix-Side: /export/synopsys/synopsys_1999_10/doc/online/top.pdf From Windows-Side: \\mdxilinx\USERS\synopsys\current\doc\online\top.pdf

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design In the Script Desired Speed: frequency … Desired Area: set_max_size … Desired Power: set_max_dynamic_power …

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Compile Options In command window: Priorities for optimization max_transition, max_fanout, max_capacitance, cell_degradation, max_delay, min_delay i.e.: set_cost_priority {max_delay max_capacitance} Optimizing power until max_area is exceeded set_cost_priority -firm_area_limit No timing constraints (only for testing) compile_power_opto_only=true

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Within Design Analyzer

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Within Design Analyzer contd

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Advanced hints Choose used cells: 1.Definition in VHDL description (ET/ITTI) then: set_dont_touch CELL_NAME 2.set_dont_use LIBRARY/CELL_NAME i.e.: set_dont_use umcl18u250t2_typ/…

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Next meeting: June, 2 th each 5 minutes, max. 5 slides, presentation of possible optimizations, results of part 2 (Synopsys) Questions? => Stephan Kubisch, Frank Sill