EKT303/4 PRINCIPLES OF PRINCIPLES OF COMPUTER ARCHITECTURE (PoCA)

Lecturers Dr. Phaklen Ehkan Dr. Muataz Hameed Rafikha Aliana A. Raof

Schedule / Contact Hours Lectures Wednesday 13:00 – 15:00 DK 8 Thursday 14:00 – 15:00 BPU 4 Lab. Thursday G2: 09:00 – 11:00 MKM7 G1: 11:00 – 13:00 MKM7

Textbook

Contents (lecture) PART 1: Introduction to Comp. Architecture (1 &2) PART 2: Foundation to Comp. Architecture ( 3 ) PART 3: Computer Memory System ( 4, 5 & 6) PART 4: Central Processing Unit (CPU) Basics (12 & 13) PART 5: Processor Internals ( 14 & 15) PART 6: Enhancing CPU Performance (16 & 17) PART 7: CPU Externals ( 7 ) PART 8: Practical Embedded CPUs ( 8 & HDESCP)

VHDL as Hardware Description Language (HDL) Its Coding NOT programming…….Okay? Altera Quartus II as a CAD Tool development platform Laboratory

Test, Quiz & Assignment = 30% Lab. Project = 20% Final Exam = 50% Assessment

9 Part I: Introduction to FPGA

10 FPGA evolutionProgrammable logic devicesField programmable gate arraysFPGA design techniquesDesign constraints using FPGAs Why FPGAs?An FPGA Primer

11 1 Higher level of performance 2 level of optimization in the hardware design required 3 Flexible processor option 4 Specific hardware functions and custom hardware design 5 complex controller and specific hardware functions 6 Density 7 Future Modification Why FPGAs?

12 FPGA evolution An FPGA Primer

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14 PAL Programmable logic devices An FPGA Primer 1 Array of logic gates 2 Array of connections 3 Small number of flip-flops (usually <10) 4 Able to implement small state machines

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16 CPLD Programmable logic devices An FPGA Primer 1 Developed to address the limitations of simple PAL devices 2 Same basic principle as PALs 3 Had a series of macro blocks (each roughly equivalent to a PAL) 4 Connected using routing blocks

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18 FPGA An FPGA Primer 1 Dynamic array of gates, the FPGA uses the concept of a Complex Logic Block (CLB) 2 Each logic block can be configured optimally 3 CLB has a Look-Up Table (LUT) that can be configured to give a specific type of logic function 4 A clocked d-type flip-flop that allows the CLB to be combinatorial or synchronous 5 A typical FPGA will have hundreds or thousands of CLBs 6 Modern FPGAs have enough capacity to hold a number of 32-bit processors on a single device

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22 Xilinx

23 Altera

24 Basic FPGA structure

25 Stratix V FPGA Architecture and Features

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27 ALTERA DE2 BOARD

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35 FPGA design techniques An FPGA Primer 1 Mapping: Logic functions mapped onto CLBs 2 Placement: CLBs placed on FPGA 3 Routing: Routed connections between CLBs Connected using routing blocks

36 Design constraints using FPGAs An FPGA Primer FPGAs obviously have a limited number of logic blocks and routing resources, and the designer has to consider this.

37 Current applications 1 Network 2 DSP 3 Parallel processing 4 Hardware emulation 5 Reconfigurable computing 6 Education 7 SoC 8 Embedded system

38 IP 1 Microprocessors 2 Filter 3 Communication elements 4 Arithmetical functions 5 Peripheral controllers 6 DSP functions

39 Digital Devices on the Scale of Programmability and Specialization

40 FPGA Design Steps

ORGANIZATION AND ARCHITECTURE 41

42 Programmer Logical execution of a program Instruction set, number of bits, I/O mechanisms, and techniques for addressing memory…. Computer Architecture Operational units Their interconnections Control signals, interfaces and the memory technology used…. Computer Organization

43 STRUCTURE AND FUNCTION

44 A Functional View of the Computer

45 Possible Computer Operations (1/2)

46 Possible Computer Operations (2/2)

47 STRUCTURE

48 Computer: Top-Level Structure

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