SiTCP and possibility of collaboration for Accelerator Control and Data Acquisition T. Obina, KEK 16/Jun/2011 EPICS Collaboration Meeting, NSRRC, Hsinchu, Taiwan

Purpose of Discussion Short Introduction of “Silicon TCP” (SiTCP) Discuss possibility of collaboration/knowledge sharing This slide is only a memo

What is SiTCP? TCP on FPGA – You can connect FPGA directly to the Ethernet – Without Hard/Soft core CPU Developed by Tomohisa Uchida – KEK, Physics Department Paper – IEEE Transactions on Nuclear Science. vol. 55, no. 3, , pp IEEE Transactions on Nuclear Science. vol. 55, no. 3, , pp As fast as hardware limit

Dr. Uchida’s Motivation Why he developed it by himself? It is very dangerous if you depend on a specific company’s technology. Minimize the effect of “Trend” or “Industry World”. For Example, – IP core supplied by a company  He found a bug, and report it. But the company did not fix it. – Original interface of a company  No compatibility between old and new product. – Developed by a tool of a company  Discontinued. Most resources cannot be used anymore.

What is “Next Standard” Bus? CAMAC/VME/PCI/cPCI PCIe? xTCA ? No one knows the future. However, TCP may not die.

SiTCP characteristics / specification Looking from FPGA Side, it looks like a FIFO Looking from Client(PC) side, it looks like a Server Small footprint Primary development target – Data Acquisition for Physics (High Energy) Experiment

Example Extensible (Can process many channels) No data loss, High throughput is important Detector PMT, etc Analog Front-end Circuit SiTCP Detector PMT, etc Analog Front-end Circuit SiTCP SWSW PC "Virtual Pipe Network" of the data can be achieved FPGA

Interface to SiTCP SiTCP has Two interfaces Fast FIFO: use TCPlike Data Bus Slow Control: use UDPlike Control Bus Ethernet PHY Initial development started for Virtex 2 (100Mbps) and moved to Virtex 4 (1Gbps) GMII SiTCP FIFO for TCP Slow Control Refer to Paper

Simple Test

My Test setup PC Development Laboratory LAN PC Ethernet Client Desktop PC Windows XP Note PC (Fujitsu) ML403 Evaluation Board RS232 JTAG 1Gbps Ethernet (crossover cable) WindowsXP or Linux(kernel2.6)

ML403 Evaluation Board PHY Marvell Alaska 88E1111 PC FPGA Xilinx Virtex4 (XC4VFX12) GMII SiTCP (Server) 1000BASE-T TestData Generator FIFO

Result : Dependence on recv buffer size with Linux, 948Mbps are achieved without any tuning

Result : Long term stability, distribution, etc Measure the transfer rate for 20min (measured as 10 sec average transfer rate) Distribution Measured on Linux

Result : 1 sec average Not on the realtime OS.

Application Readout for Neutron detectors Super Kamiokande Neutron Imaging Detector, and many physics experiments ….. Recently, Synchrotron Radiation user is contributing. (Dr. Kishimoto, KEK-PF)

Can we use it for accelerator control? Academic use Open

Question / Request Xilinx is supported. How about Altera? – For now, SiTCP is spplied as netlist for Xilinx – Maybe possible, but needs time…. Confirm it later. Speed : 1G is enough? – 10G is better, 1G is still quite useful Using build-in SERDES, we can interface optical fiber Latency Number of Server Session : 1 SiTCP Client Radiation Hardness?

Possibility of Collaboration I don’t block. (I’m not an representative of Dr. Uchida) I think it might be a good idea to have ‘small community’ for “SiTCP for accelerator control and data acquisition” Dr. Uchida is very powerful person, but human. Mailing List is better to avoid many people ask same question to him. Let’s share the knowledge. Wiki – discussion, summary, FAQ, documentation, etc License, NDA, Terms of use ? … maybe not. confirm. SiTCP on Open Source Hardware

Send Open Source to Dr. Uchida ? – Information at first. If he has interest, Hardware Client  FPGA data transfer Measurement of Latency In some detector application, 10G is already used. Possibility to open the source code in the future.

References SiTCP Homepage – (Japanese) Open Source Consortium of Instrumentation – Bee Beans Technology –