An Energy-Efficient Reconfigurable Multiprocessor IC for DSP Applications Multiple programmable VLIW processors arranged in a ring topology –Balances its functionalities between ASICs and general-purpose digital signal processors –Distributed memories along with direct inter-processor communications through register files –Flexible choice of computing resources Energy-efficient DSP applications can be achieved by exploiting its multi-level reconfigurable architecture –Efficient mapping of algorithms onto the multiprocessor –Inside each processor, computation modules, e.g. multipliers, can be turned off by the instructions to improve the energy-efficiency –Scalable datapath provides a means of trading off performance vs. power efficiency –Memory localization through distributed memories also contributes to power savings

Variable word-length 20-tap FIR and 8-point FFT (16-, 24- and 48-bit) –In 16- and 24-b resolution, ring A in use and ring B in “sleep mode”; in 48-b mode, both rings are active—ring A for 24 MSBs and ring B for 24 LSBs –Booth multipliers used in 16-b mode; serial multipliers employed in 24- and 48-b modes –Multipliers are active only for the multiplication with W 8 1 and W 8 3 in the FFT Reconfigurable Viterbi decoder (K = 6 to 9, r = 1/2 and 1/3) –Efficient ACS implementation and path metric memory localization Energy-Efficient DSP Applications on the Multiprocessor IC

(c) Viterbi decoder: power consumption vs. VDD (d) Viterbi decoder: maximum throughput vs. VDD (a) FIR & FFT: power consumption vs. VDD(b) FIR & FFT: maximum throughput vs. VDD Results and Conclusion Conclusion: the multiprocessor IC achieves performance close to ASIC solutions while possessing a degree of flexibility available only in general-purpose digital signal processors 48-b FIR 48-b FFT 24-b FIR 24-b FFT 16-b FIR 16-b FFT 16-b FIR 24-b FFT 24-b FIR 48-b FFT 48-b FIR