Marlon Barbero – Centre de Physique des Particules de Marseille Rad-Hard Active Pixel Sensors for HL-LHC Detector Upgrades based on HV-CMOS Marlon Barbero – Centre de Physique des Particules de Marseille barbero@cppm.in2p3.fr 13th Topical Seminar on Innovative Particle and Radiation Detectors 7 - 10 October 2013, Siena, Italy

ATLAS tracker upgrade plan New insertable b-layer (IBL) New Al beam pipe New pixel services New insertable b-layer (IBL) New Al beam pipe New pixel services Fast TracKing (FTK) for level2 trigger All new tracker (baseline: long strips /short strips / pixels) Possible level1 tracker IBL: On-going construction phase!

HL-LHC environment challenge HL-LHC targets: 14TeV; Luminosity: 5.1034 cm-2.s-1 / 3000 fb-1 in ~7 years Consequences for trackers: High radiation for the innermost layers (~5cm): ~1.1016 neq.cm-2 / ~1GRad  rad-hardness! (note: ~50-100MRad at 25cm) High occupancy: cope with of order <140> pile-up events / bunch-crossing  high granularity! fast! Huge surface to cover: of order 200m2  reduction in costs!

Using Hybrid Detectors n-in-n or n-in-p with reduced drift distance (3D or thin silicon). DSM rad-hard IC (a la IBL FE-I4 -130nm- or reduced feature size 65nm?). Valid option: should work (after development). Drawback: 1- Price of hybridization / of non-standard sensors (yield?) and for a large area. 2- Will stay rather thick. 3- High bias voltage. 4- Deep charge collection leads to difficult 2-track separation in boosted jets.

Principle of HV-CMOS process An n-well in p-substrate diode, populated with CMOS (first stage amplifier or more complex). CMOS! e.g. 1st stage amplifier n-well in p-substrate diode n-well biasing depletion zone around nwell: charge collected by drift resist~10Ω.cm

ATLAS HV-CMOS Collaboration Bonn University: M. Backhaus, L.Gonella, T. Hemperek, F. Hügging, H. Krüger, T. Obermann, N. Wermes. CERN: M. Capeans, S. Feigl, M. Nessi, H. Pernegger, B. Ristic. CPPM: M. Barbero, F. Bompard, P. Breugnon, JC. Clemens, D. Fougeron, J. Liu, P.Pangaud, A. Rozanov. Geneva University: D. Ferrere, S. Gonzalez-Sevilla, G. Iacobucci, A. Miucci, D. Muenstermann. Goettingen University: M. George, J. Grosse-Knetter, A. Quadt, J. Rieger, J. Weingarten. Glasgow University: R. Bates, A. Blue, C. Butter, D. Hynds. Heidelberg University: I. Peric (original idea). LBNL: M. Garcia-Sciveres.

Process Main Characteristics CMOS electronics inside deep n-well. Negatively biased substrate leads to ~8-10μm depletion zone  charge collection by drift. Small feature size + relatively low complexity of in-pixel logic  small pixel. 1st stage signal amplification on-sensor (low capacitance  low noise). Featuring: 1- electronics rad-hard (DSM technology). 2- sensor rad-hard (small depletion depth, small ΔNeff). 3- low price (standard CMOS process). 4- low material budget (can be thinned down). 5- low maximum bias voltage (moderate substrate resistivity). 6- fast (electronics on sensor). 7- good granularity (1st prototype 33×125μm2, can go down). HV2FEI4p1/-p2 in AMS180nm HV-CMOS.

HV2FEI4 series -p1: Proof of principle. -p2: Rad-hardness enhanced. 2.2×4.4 mm2. 60columns×24rows. pixels: 33×125μm2. pads to realize various operation modes: Standalone measurement possible. CCPD: Capacitively coupled to pixel IC. Bonded to strip readout IC. IO for CCPD strip pads pixel array w. transmission pads IO for strips

Readout -a la strips- Readout: use HV-CMOS sensor in combination with existing powerful IC by connecting HV-CMOS pixels in various ways. e.g. pixels can be summed up as “virtual strips”, with hit position encoded as pulse height. Pixel hit map from strip information (note the shadow of a wire)

Readout -with larger pixels- Combine 3 pixels together to fit one FE-I4 pixel (50×250μm2), with HVCMOS pixels encoded by pulse height. Capacitive coupling OK: gluing! (perspective to avoid bump-bonding?) The tiny HV2FEI4p1 prototype glued on the large FE-I4

HV2FEI4p1 on FEI4 90Sr-source. Readout through FE-I4. kHz rate recorded!

Sub-pixel encoding principle unirradiated sensor Works on single pixel cells. Sub-addresses well separated in ToT histo. Sub-pixel 2 3 sub-pixels on Sub-pixel 1 Sub-pixel 3 Three values for the addresses decoded by the FE-I4 pixel

HV2FEI4p1 Recorded routinely 90Sr and 55Fe spectra. Degradation at 80MRad proton irradiation (dead at 200MRad!) Discri

Bulk damage Small depletion depth + Neff > 1014.cm-3 bulk rad-hard? Non-ionizing radiation at neutron source (Ljubljana) to 1.1016 neq.cm-2. occupancy in 10 minutes No source With 90Sr leakage current increase (as expected) sensor works at room T after 1016 neq.cm-2. (scintillator trigger used) Note: 30 days annealing at room temp

TID issue HV2FEI4p2 Few pixel flavors with enhanced rad-hardness: guard rings, circular transistors… (different pixel types lead to different gains -expected-). 55Fe spectra, unirradiated “rad-hard” “normal” different gains

TID issue HV2FEI4p2 After 862 MRad Xray (annealing included 2h at 70C each 100MRad), after parameter retuning, amplifier gain loss recovered to 90% of initial value Relative preampli amplitude variation as function of dose Recovery at 862 MRad (NOT 900MRad)

Conclusion Principle: Firmly established. Various types of readout demonstrated, among which capacitive coupling through gluing to FE-I4. Prospects for: Small pixels, less material, cheaper, large area… Need further studies on radiation hardness, but positive indications of radiation tolerance. Need efficiency / spatial resolution studies  test beam. Need optimization to establish geometry & architecture. Discussion on new larger size prototype to realize currently on-going.

Outlook Hybrid solution vs monolithic for future trackers? 65nm vs HVCMOS? For the monolithic case, our collaboration has started to look into other processes: M5 M4 M3 M2 M1 Super Contact M6 Bond Interface Tier 2 Tier 1 (thinned wafer) Back Side Metal sensor T3-MAPS (LBNL) IBM 130nm 1640 electrons (assuming collected by one pixel) DMAPS (Bonn) ESPROS 150nm GFMAPS (CPPM) GF 130nm

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New monolithic sensors on a fully isolated substrate Spectrum of Fe55 (X-ray) and Sr90 (e-), obtained from a 10mX10m single pixel. We have exploited a new CMOS substrate isolation implant to implement a monolithic radiation detector. Because the substrate is completely junction-isolated from the active wells, it can be biased at larger negative voltages than would be possible in a standard process. This not only permits true 100% fill factor but also improves the sensor performance. Preliminary results will be shown.

Outlook another 3D approach We submitted on June 2013 a new HV2FEI4 version in GlobalFoundries 0.13µm BCDLite technology. The chip is 100% compatible with the HV2FEI4 chip, and could be easily tested. Despite some small failures, the chip works at -30V The HV2FEI4 could be use on a complex and advanced monolithic 3D chip, including analog sensor and digital post-processing parts M4 M5 M3 M1 M2 Super Contact M6 Bond Interface Tier 2 Tier 1 (thinned wafer) Back Side Metal sensor

EPCB01 – Depleted monolithic pixel chip Features: Technology: ESPROS Feature size: CMOS 150 nm High resistive N-type bulk (~ 2 kΩ cm) High voltage at sensor domain possible (~ 10 V) P-type well to integrate CMOS electronics 6 metal layers Chip is thinned down to 50 µm Full depletion can be achieved New Physicist’s dream??

Source scan Fe55 Fe55 used for calibration of Sr90 plot Sr90 MPV ~2400 electrons (~ 4200 electrons expected for ~ 50 µm silicon) → rest of the charge is collected by other pixels (clustering)