The ARM Programmer’s Model Jacob Huerta, Ryan Crell, and Veronica Hohe 1/30/2015

Outline ARM Registers Von Neumann Cycle Sequence CPSR Memory Standard ARM vs. Thumb ARM Instructions ARM Instructions Supervisor Mode/Kernel Mode Exceptions 1/30/2015

ARM Registers 1/30/2015

ARM Registers Instruction set = operations to change system state State = data items in processor’s visible registers/systems memory Multiple invisible registers in a processor 1/30/2015

ARM Registers User-level programming 15 general purpose registers PC CPSR System-level programming/exceptions Remaining registers 1/30/2015

Von Neumann Cycle Sequence 1/30/2015

Von Neumann Cycle Sequence 1/30/2015

CPSR 1/30/2015

ARM CPSR Control Bits Protected from user-level programs Mode T IF Control the processor mode Bits 0-4 (must be a valid mode) T Control the instruction set State bit IF Enables control interrupt Bit 6 is FIQ disable and Bit 7 is IRQ disable 1/30/2015

ARM CPSR Flag Bits Condition Code Flags NZCV N (“Negative flag”) 0/1 = value is positive/negative Z (“Zero flag”) 0/1 = result is non-zero/zero C (“Carry flag”) 0/1 = “extends” for shift/”borrows” for subtraction V (“Overflow flag”) 0/1 = no overflow/overflow caused by last arithmetic operation 1/30/2015

ARM CPSR Unused Bits Unused bits Reserved State preserved when changing the flag or control bits Should not be altered by programs Should not rely on them when checking the PSR status Might read as 1’s or 0’s in future processors 1/30/2015

ARM Memory Organization 1/30/2015

ARM Memory Organization View memory as linear array of bytes numbered from 0 to 232-1 Store data items in Byte (8 bits) Half-word (16 bits) Word (32 bits) Align words on 4 bytes Organize in little-endian style 1/30/2015

ARM Instructions 1/30/2015

ARM vs. THUMB Instructions 32-bit instruction set 3-data address instructions 16 general purpose registers 16-bit instruction set 2-data address instructions 8 general purpose registers “Less regular” instructions Higher code density High performance 1/30/2015

ARM vs. THUMB Instructions Not a “complete” architecture Supports ARM architecture The T bit in CPSR toggles the interpretation 1/30/2015

ARM vs. THUMB Instructions 1/30/2015

ARM Instructions Load-store architecture Processes only values stored in registers and instructions Performs operations on these values Stores results in register Affects memory using only load and store instructions Inability to perform memory-to-memory operations Instructions Data processing: between registers (add, sub, etc.) Data transfer: between registers and memory (load, store) Control flow: execution of instructions (branches, link, supervisor calls) 1/30/2015

Supervisor Mode/Kernel Mode 1/30/2015

Supervisor Mode/Kernel Mode User with supervisor privileges can use system calls to affect Kernel code Device drivers Privileged code User program with IO access permissions Unprivileged code User programs 1/30/2015

Exceptions 1/30/2015

Exceptions Normal execution is paused to handle events like Systems calls Interrupts generated by external sources Undefined instructions Traps 1/30/2015

Exception Handling Save current state is Copy PC into register rl4_exc Copy CPSR into register SPSR_exc Register r13_exc = pointer to memory stack to store user registers Set processor operating mode to exception mode 1/30/2015

Exception Handling Set PC to value between 0x00 and 0x1C depending on exception type Restore user registers from memory stack Restore (adjusted) PC and CPSR 1/30/2015

Input/Output (I/O) System 1/30/2015

Input/Output (I/O) System I/O peripheral Device mapped to memory Device registers treated as memory locations by system Given interrupt support (make interrupt requests) Normal interrupt (IRQ) = most requests Fast interrupt (FIQ) = time-sensitive/critical requests Direct Memory Access (DMA) External to ARM processor Handles high-bandwidth I/O traffic 1/30/2015

References (2001). “The Thumb Instruction Set.” Web. 2001. January 28, 2015. http://paulkilloran.com/arm/Lecture_7.pdf (2014). “About processor exceptions.” ARM. Web. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471g/BABGCFHB.html. (2014). “Exception handling process.” ARM. Web. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471g/BABGCFHB.html. (2014). “Load/store architecture.” Wikipedia. Web. August 4, 2014. http://en.wikipedia.org/wiki/Load/store_architecture. (2014). “Protection ring.” Wikipedia. Web. December 30, 2014. http://en.wikipedia.org/wiki/Protection_ring. (2014). “Reserved bits.” ARM. Web. August 4, 2014. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0229c/ch02s07s03.html (2014). “Trap (computing).” Wikipedia. Web. April 30, 2014. http://en.wikipedia.org/wiki/Trap_(computing). Furber, S. (2000). ARM system-on-chip architecture. Harlow, England: Addison-Wesley. (2014). Gibson, J. (2011). ARM assembly language: An Introduction (2nd ed.). Lexington, KY: The Author. 1/30/2015

Questions? 1/30/2015