EE 587 SoC Design & Test Partha Pande School of EECS Washington State University

SoC Physical Design Issues Wire Capacitance

Technology Scaling Effects At 0.5um and above: Simple capacitance At 0.35um and below: Resistance At 0.18um and below : Coupling Capacitance At 0.10um and below: Inductance t v I avg.....

Interconnect Capacitance Profiles Total capacitance can be decomposed into three components:  Area capacitance  Lateral capacitance  Fringe capacitance Height ab o v e Substrate Vertical spacing between conductors C total = C area + C lateral + C fringe H S W T H Horizontal spacing between conductors

Wire Dimensions T=wire thickness, H=vertical wire separation, S=horizontal wire separation, W=wire width, L=wire length T and H are fixed parameters based on the fabrication process W, S and L are under the designer’s control

Computation of Area Capacitances Metal 1 Metal 2 CaCa CaCa Area capacitance per unit length can be simply calculated using: C a =  ox W = 0.035fF/um (W/H) H W H

Computation of Lateral Capacitances Metal 1 Metal 2 Closely spaced wires CLCL CLCL Lateral capacitance per unit length for closely spaced wires can be calculated using: For widely spaced wires, C L drops off as 1/S C L =  ox T = 0.035fF/um (T/S) s T S

CaCa CaCa Computation of Fringe Capacitances Metal 1 Metal 2 Widely separated wires CfCf CfCf T H For widely spaced conductors

CaCa CaCa Computation of Total Capacitances Metal 1 Metal 2 CfCf CfCf For closely spaced wires, assume fringe is small For widely spaced wires, assume lateral is small For medium spaced wires, C f and C L will both exist and vary with S C total = 2C a + 2C L = 0.2fF/um T CLCL CLCL C total = 2C a + 2C f = 0.2fF/um

Wire Capacitance Trend Inter-metal capacitance

Coupling Effects New model of interconnect Each driver connected to A,B,C or D can act as aggressor Coupling capacitance could inject noise or affect delay A B C D Agressor Victim C CgCg

First-Order Delay Analysis If aggressor is not switching If aggressor switches in same direction. If aggressor switches in opposite direction: “Miller” factor Multiplying factor ranges from 0 to 2 (Actual range is –1 to 3) Rup CgCg Rdn C CgCg Rup C g Rdn C C V DD

Signal Integrity Effect on Timing Victim net without coupling Victim net with coupling delay Aggressor net Victim net without coupling Aggressor nets Victim net with coupling delay Net delay due to a single coupled aggressor net Net delay due to multiple coupled aggressor nets Performance impact: 300 picosecond delay (3% of a clock cycle) Performance impact: over 2 nanosecond delay (20+% of a clock cycle)

First-order Noise Analysis Assume that aggressor and driver resistances are negligible If V 1 changes by V DD, what change  V do we expect to see at the internal node in the worst case? Produces results that are somewhat pessimistic  V 1 V2V2 CcCc CgCg  V 2 = C c V dd C c + C g V 2 = CcV1CcV1 C c + C g  V 2 = C c  V 1 C c + C g C c (V 1 - V 2 ) = C g V 2 Looks like the feed through equation

2nd-order Noise Analysis Rup CgCg Rdn C V DD How much noise is actually injected into the victim line by a voltage transition on the aggressor line? aggressor victim Treat RC problem as a resistive divider: V O = Z dn V DD Z dn + Z up Z dn Z dn + Z up = R dn 1 + sC g R dn R dn 1 + sC g R dn + (R up + 1/sC c ) = sC c s 2 R up C c C g + s(C c + C c R up /R dn + C g ) + 1/R dn Vdd C CgCg CgCg

Capacitive Coupling What is the maximum value of spike? Depends on values of R,C  Worst case would be large C c, small C g, small Rup, large Rdn Look at some limits: V peak < Vdd*Rdn/(Rdn+Rup) (set Cc infinite, Cg=0) V peak < Vdd*Cc/(Cc+Cg) (set Rup=0, Rdn infinite) Voltage spike response depends on RC ratios  going up, time constant is R up C c  going down, time constant is R dn (C g + C c ) Rup CgCg Rdn C V DD Rdn*(Cg+Cc) < RupCc Amplitude based on resistor ratio Rdn*(Cg+Cc) > RupCc Amplitude based oncapacitance ratio

Wire Model of a Bus For an inner wire the total bottom capacitance is For an outer wire

CIBD ConditionsVictim Capacitance The victim and aggressors switch in the same direction The victim and one aggressor switch in the same direction and the other aggressor remains quiet The victim switches and both aggressors are quiet The victim and one aggressor switch oppositely, while the other aggressor is quiet The victim and both aggressors switch oppositely

Signal Integrity Issues at FF’s What happens if a glitch occurs in a clock signal? Flip-flop captures and propagates incorrect data Could view any signal that, if glitched, could cause a logic upset as a “clock” signal Need to space out clocks/signals or shield them DQ Clk Positive-Edge Triggered Flip-Flop Clk

Signal Integrity Issues at FF’s What happens if a glitch occurs in data signal? Flip-flop captures and propagates incorrect data Need to insure that data signal is stable during FF setup time Shielding with stable signals or spacing is needed DQ Clk Positive-Edge Triggered Flip-Flop Clk

Reducing Coupling Capacitance Space out the signals as much as possible, but it cost area. (a) higher coupling cap./less area (b) lower coup. cap./ more area Use Vdd and Gnd to shield wires wherever required (a) higher coupling cap./less area (b) higher tot. cap./ more area AB AB AB AB Vdd Gnd

M5 via5 M4 via4 M3 via3 M2 via2 M1 cont silicon Reducing Coupling Capacitance Copper and low-k dielectrics try to reduce k from 3.9 to 2 – lower coupling caps  better electromigration reliability   Multiple Levels of Metal Cu Low-k Dielectrics  

Crosstalk Avoidance through Coding A wire has maximum coupling if and only if it has a rising (falling) transition when both its neighboring wires have falling (rising) transitions.

Forbidden Pattern Codes Avoiding bit patterns 010 and 101 from every codeword. However, encoding all bits at once using this is infeasible for large buses due to prohibitive complexity of the codec circuits. Therefore, partial coding is employed, in which the bus is broken into sub-buses of smaller width which are encoded into sub channels. These sub-channels are then combined in such a way so as to avoid crosstalk delay at their boundaries.

Forbidden Adjacent Boundary Pattern Condition codeword with 01 pattern does not transition to a codeword 10 pattern at the same bit boundary.

Forbidden Overlap Condition The codebook cannot have both 010 and 101 appearing centered around any bit position. Data bitsCode bits d3d2d1d0c4c3c2c1c

Overall scheme [31-0] Input FOC 4-5 (1) FOC 4-5 (2) FOC 4-5 (7) FOC 4-5 (8) [3-0] [4-0] [3-0] [4-0] [3-0] [4-0] [39-0] Output Clock Reset

Hamming Codes For SEC Hamming code, 3 check bits are added to the 4 information bits

Dual Rail Code For a bus of k information bits, m=k+1 check bits need to be added The k+1 check bits are defined as Check bits for i= 0 to k-1 are a copy of the respective data bits, whereas check bit is a data parity bit

Delay Comparison

Codec Implementation of Coder & Decoder (Codec) is important Area overhead Extra energy dissipation Reliability comes at a cost

Summary Crosstalk has serious effects on signal reliability in UDSM era Only shielding or other traditional techniques are not sufficient CAC is a promising solution We need to consider area-power tradeoff