ECEN 248 Lab 6: De-Bouncing, Counters & LCD Display Control names Dept. of Electrical and Computer Engineering

Lab 6 in Brief Design an eight bit counter Bouncing counter De-bouncing counter Learn about configuring the LCD display

Sequential Logic We are only handling the combinational logic circuits in the previous labs Starting from Lab 5, we will deal with the sequential logic circuits In sequential logic circuits, the output will depend on not only the current input, but also the previous inputs. Always driven by clock pulses

Counter Using sequential logic to count clock events

Push Buttons A push button is a mechanical switch and rely on mechanical contact to generate an electrical pulses

Switch Bouncing When you push the button, it will not instantly give a 0 (or a 1 when inverted); instead, the voltage will fluctuate in a middle region at first. Voltages in the middle region are still interpreted (quantized) as 1’s and 0’s, so the output will “bounce” between 0 and 1 until the value settles. That means even you only push the button once, there will be multiple rising edges generated. Push Release

De-Bouncing Need to get rid of the bounces and get the “clean” signal Two methods RS latch based debouncing Needs two buttons Sampling based de-bouncing One button

Method 1: SR Latch Use the SR latch to clean the bouncing signal

Method 2: Sampling based debouncing always @ (posedge clock) if (reset) begin new <= noisy; clean <= noisy; count <= 0; end else if (noisy != new) begin new <= noisy; count <= 0; end else if (count == 500000) clean <= new; else count <= count+1; 9

LCD Display Two Verilog modules lcd_disp Given in the zip file for lab 5 You can reuse this module Lcd_int You need to design a specific lcd_int module for each lab Determine data display location in LCD One characters  8bit (check decoder chart Fig. 6.9) Outputs 32 eight-bit sequences for 32 characters in LCD

Lab 6 To-Do list Design 1 Configure LCD display Design 2 Design a non-debounced counter Design 3 Design a count-up counter and a count-down counter using non-debounced signal Design 4 Design a SR-latch based debounced up-counter Design 5 Design a sampling-based debounced up-counter

Deadlines Today 2 Weeks later Work on Lab 6 Lab 6 Post-Lab due Lab 7 Pre-Lab due at the beginning of class