Tom McMullen Week 5 4/3/2013 – 8/3/2013. LETI wafer thinning project flow Phase 1 IDProject NameOwnerDaysStartEnd 3-Feb10-Feb17-Feb24-Feb3-Mar10-Mar17-Mar24-Mar31-Mar5-Apr12-Apr19-Apr26-Apr.

Slides:



Advertisements
Similar presentations
ASE Flip-Chip Build-up Substrate Design Rules
Advertisements

Center for Materials and Electronic Technologies
ECFA-DESY meeting, Krakow, 16 th September 2001Václav Vrba, Institute of Physics, AS CR 1 Václav Vrba Institute of Physics AS CR, Prague Silicon pad sensors.
Hybridization studies at Fermilab Prototype detectors –Readout chip mated to sensor –Experiences with both single dies and 4” and 6” wafers using Indium.
Bump bonding follow up from AUW R. Bates & F. Hügging.
UK – quad module. Experience with FE-I4 UK groups relatively new to ATLAS pixel Have 5 USBPix systems up and running now – Glasgow, Edinburgh, Manchester,
CERN 30 Aug 2002ATLAS MDT-ASD PRR -- E. Hazen1 ATLAS MDT-ASD Integrated Circuit Production And Testing Plan E. Hazen – Boston University.
3D PACKAGING SOLUTIONS FOR FUTURE PIXEL DETECTORS Timo Tick – CERN
Tom McMullen Week 9 1/4/2013 – 5/4/2013. LETI wafer thinning project flow Phase 1 IDProject NameOwnerDaysStartEnd 3-Feb10-Feb17-Feb24-Feb3-Mar10-Mar17-Mar24-Mar31-Mar5-Apr12-Apr19-Apr26-Apr.
Tom McMullen Week 6 11/3/2013 – 15/3/2013. LETI wafer thinning project flow Phase 1 IDProject NameOwnerDaysStartEnd 3-Feb10-Feb17-Feb24-Feb3-Mar10-Mar17-Mar24-Mar31-Mar5-Apr12-Apr19-Apr26-Apr.
Tom McMullen Week 3 25/2/2013 – 1/3/2013. LETI wafer thinning project flow Phase 1 IDProject NameOwnerDaysStartEnd 3-Feb10-Feb17-Feb24-Feb3-Mar10-Mar17-Mar24-Mar31-Mar5-Apr12-Apr19-Apr26-Apr.
Sources and Uses of Funds Analysis (Comparative Balance Sheet Analysis)
20th RD50 Workshop (Bari)1 G. PellegriniInstituto de Microelectrónica de Barcelona G. Pellegrini, C. Fleta, M. Lozano, D. Quirion, Ivan Vila, F. Muñoz.
Status and outlook of the Medipix3 TSV project
Magnetic Nanofluidics ME342 Design Project Update 3 Abhishek Dhanda Kwan-Kyu Park Michael Pihulic Katherine Tsai July 27, 2006.
3D chip and sensor Status of the VICTOR chip and associated sensor Bonding and interconnect of chip and sensor Input on sensor design and interconnection.
Plans for Demonstrator Flip Chip Bonding GTK meeting 9/12/08 1.
Tom McMullen Week 3 18/2/2013 – 22/2/2013. LETI wafer thinning project flow Phase 1 IDProject NameOwnerDaysStartEnd 3-Feb10-Feb17-Feb24-Feb3-Mar10-Mar17-Mar24-Mar31-Mar5-Apr12-Apr19-Apr26-Apr.
M.Friedl, C.Irmler, M.Pernicka HEPHY Vienna
March 20, 2001M. Garcia-Sciveres - US ATLAS DOE/NSF Review1 M. Garcia-Sciveres LBNL & Module Assembly & Module Assembly WBS Hybrids Hybrids WBS.
Tom McMullen Weeks 1 and 2 4/2/2013 – 15/2/2013. LETI wafer thinning project flow Phase 1 IDProject NameOwnerDaysStartEnd 3-Feb10-Feb17-Feb24-Feb3-Mar10-Mar17-Mar24-Mar31-Mar5-Apr12-Apr19-Apr26-Apr.
G. Parès – A. Berthelot CEA-Leti-Minatec GU project status.
Tracker Upgrade Week –Sensors Meeting Sensor Production 24. July 2014 Marko Dragicevic.
FPIX_flip_chip_test module calibration tests November 14 th 2012.
Medipix sensors included in MP wafers 2 To achieve good spatial resolution through efficient charge collection: Produced by Micron Semiconductor on n-in-p.
CERN November 2008 Marcello Mannelli CMS SLHC Tracker Thin Sensor R&D with HPK CMS SLHC Tracker Thin Sensor R&D with HPK.
CERN Rui de OliveiraTS-DEM TS-DEM Development of Electronic Modules Rui de Oliveira CERN CERN hybrid production experience (or how to stay out of trouble)
1 Presentation Template: Instructor Comments u The following template presents a guideline for preparing a Six Sigma presentation. An effective presentation.
CMS Phase 2 Tracker R&D R. Lipton 3/27/2014 Module R&D Allocation: Requested ~ $320k, received ~160k – Eliminate VICTR testing (continue with FNAL funds.
VTT ASSEMBLY 5 CHARACTERISATION KATE DOONAN & RICHARD BATES 2012.
U.S. Deliverables Cost and Schedule Summary M. G. D. Gilchriese U.S. ATLAS Review Revised Version November 29, 2000.
Tom McMullen Period 3 Week 9 8/4/2013 – 12/4/2013.
1 DMAIC Define Overview Paul Grooms Black Belt in Training.
Estimated schedule, costs and number of ABC130 needed Tony Affolder.
U.S. Deliverables Cost and Schedule Summary M. G. D. Gilchriese Revised Version December 18, 2000.
DESIGN CONSIDERATIONS FOR CLICPIX2 AND STATUS REPORT ON THE TSV PROJECT Pierpaolo Valerio 1.
Status of Hamamatsu Silicon Sensors K. Hara (Univ of Tsukuba) Delivery leakage current at 150V & 350V number of defect channels wafer thickness & full.
Thin Silicon R&D for LC applications D. Bortoletto Purdue University Status report Hybrid Pixel Detectors for LC.
Tom McMullen Week 7 18/3/2013 – 22/3/2013. LETI wafer thinning project flow Phase 1 IDProject NameOwnerDaysStartEnd 3-Feb10-Feb17-Feb24-Feb3-Mar10-Mar17-Mar24-Mar31-Mar5-Apr12-Apr19-Apr26-Apr.
Sensor testing and validation plans for Phase-1 and Ultimate IPHC_HFT 06/15/ LG1.
Roadmap to the next 2015 run F. Marchetto GigaTracKer Working Group meeting Dec. 9 th 2014 a)Introductory meeting on Nov. 27, 2014 b)At that meeting several.
Tom McMullen Week 8 25/3/2013 – 29/3/2013. LETI wafer thinning project flow Phase 1 IDProject NameOwnerDaysStartEnd 3-Feb10-Feb17-Feb24-Feb3-Mar10-Mar17-Mar24-Mar31-Mar5-Apr12-Apr19-Apr26-Apr.
D. Henry / CEA-Leti-Minatec Contibuting authors : A. Berthelot (LETI) / R. Cuchet (LETI) / J. Alozy (CERN) / M. Campbell (CERN) AIDA Meeting / 08 & 09th.
MEMS Packaging ד " ר דן סתר תכן וייצור התקנים מיקרומכניים.
Phase 2 Tracker Meeting 6/19/2014 Ron Lipton
L. Greiner1IPHC-LBNL Phone Conference 07/10/2012 STAR IPHC-LBNL Phone Conference News and updated ladder testing.
Giulio Pellegrini 27th RD50 Workshop (CERN) 2-4 December 2015 Centro Nacional de MicroelectrónicaInstituto de Microelectrónica de Barcelona 1 Status of.
ASE ASE Flip-Chip Laminate Substrate Design ASE Flip-Chip Laminate Substrate Design Date : 07/15/03 Rev. H.
G. Ruggiero / TOTEM 1 Si Edgeless Detectors in the RPs Edgeless detector (on the old “AP25 module”) active edges (“planar/3D”) planar tech. with CTS (Current.
Timepix test-beam results and Sensor Production Status Mathieu Benoit, PH-LCD.
Status report Pillar-1: Technology. The “Helmholtz-Cube” Vertically Integrated Detector Technology Replace standard sensor with: 3D and edgeless sensors,
Big Lottery Fund ESIF BBOBBO PROGRAMME DEVELOPMENT FUNDING.
The medipix3 TSV project
B => J/     Gerd J. Kunde PHENIX Silicon Endcap  Mini-strips (50um*2mm – 50um*11mm)  Will not use ALICE chip  Instead custom design based on.
L. Bosisio - 2nd SuperB Collaboration Meeting - Frascati SuperB SVT Update on sensor and fanout design in Trieste Irina Rashevskaya, Lorenzo.
Sensors Pixel dimension 300 x 300 μm2 Standard p-in-n sensors
T. Bowcock University of Liverpool
Hybrid Pixel R&D and Interconnect Technologies
Alternative process flows for reduction of steps
Highlights of Atlas Upgrade Week, March 2011
ALICE PD group meeting Andrea Francescon.
Sensor Wafer: Final Layout
Micro-cooling devices for LHCb Velo CERN
Development of thin pixel modules using novel 3D Processing techniques 9th Trento Workshop, Genoa 2014 T.McMullen1, G.Pares2, L.Vignoud2, R.Bates1, C.Buttar1.
2S module geometry updates Module positioning concepts
CERN & LAL contribution to AIDA2020 WP4 on interconnections: Pixel module integration using TSVs and direct laser soldering Malte Backhaus, Michael Campbell,
Presentation Test. Second Slide Third Slide It worked.
UCSB Dicing, Wire-Bonding and Board Assembly
1. Get specs from customer Cost out the solution Decide discount strategy Assemble proposed response Approve proposed response.
Presentation transcript:

Tom McMullen Week 5 4/3/2013 – 8/3/2013

LETI wafer thinning project flow Phase 1 IDProject NameOwnerDaysStartEnd 3-Feb10-Feb17-Feb24-Feb3-Mar10-Mar17-Mar24-Mar31-Mar5-Apr12-Apr19-Apr26-Apr 1.0Thin Wafer AssembliesT. McMullen01-Feb30-Sep Week 1Week 2Week 3Week 4Week 5Week 6Week 7Week 8Week PHASE 1 - Layout and mask production, first 2 wafers with microbumps delivered to AdvacamLETI - 3D101-Feb29-Mar LETI accpets CERN proposal 1.1.1Send gds to LETIT. McMullen51-Feb8-Feb Send 2 FEI4b wafers to LETIR. Bates51-Feb6-Feb Confirm step size on wafer and centre ofset variation on waferLETI51-Feb6-Feb Layout and mask productionLETI101-Feb11-Feb Deliverable 1: Microbumb gds files First 2 wafers with micro bumps delivered to AdvacamLETI4912-Feb2-Apr Deliverable 2: First 2 wafers with micro bumps delivered to Advacam Current Deliverable Target not met

Action List Phase 1 and 2 ActionWhatWhoWhenComment 6Further funding for flip-chip processRbates\Cbuttar31/3/2013Richard has confirmed this is all in place 7Bow measurement set-upTMcM31/2/2013visit SMC and set up program for bow measurement 8Sensors for flip chippingAll31/3/2013Sensor availablilty for flip-chip process - Meeting rqd 9Assembly probe test solutionTMcM19/3/2013Pobe test solution for flip-chipped assemblies - yield maps 10FEI4B probe card and probe set-upRbates/TMcM19/3/2013FEI4B test solution for assembly testing yeild maps 11Experience with FEI4A probe card set-upRbates/TMcM19/3/2013 FEI4A probe card set-up and testing of assemblies on Wentworth

Highlights and issues  Cash for flip-chip bonding We will need this further funding by the end of phase 1 (week 9 from Gant on previous slide) to test the LETI micro-bumps Richard has confirmed that this is OK  Bump gds design completed and mask delivery due end of next week LETI are confident they will have delivered wafers to ADVACAM by deliverable date.  Meeting required to discuss sensor availability for the flip-chip process Amount of sensors for flip-chipping – good statistical analysis required for micro-bump yield – Richard and I have begun discussions on this. IBL TDR bump spec: ○ Pitch = 50um ○ Bump density = 26,880 per ROIC ○ Defect rate < ○ ROIC thickness <200um FEI4b Assembly testing ○ FEI4b probe card required ○ Test equipment/apparatus required ○ Semi-auto testing solution required for assemblies

Wafer Inventory Wafer #Wafer IDYieldPurposeComment 1VMB8WDHG= 34, y=17, R=8, B=1Full thickness micro-bump testDelivered to LETI. High-yielding die. Micro-bump yeild testing on assemblies 2V6B8WUHG= 43, y=13, R=4, B=0Full thickness micro-bump testDelivered to LETI. High-yielding die. Micro-bump yeild testing on assemblies 3VUAYCRH First technology run. Run 2 Received at Glasgow Wafer thinning to 100microns. Used for thermal cycling bow measurements at SMC. Ship to LETI 4ABPJXGH First technology run. Run 2 Received at Glasgow Wafer thinning to 100microns. Used for thermal cycling bow measurements at SMC. Ship to LETI 5 Second technology run. Run 3Wafer to be identified and delivered to glasgow 6 Second technology run. Run 3Wafer to be identified and delivered to glasgow 7 Third technology run. Run 4Wafer to be identified and delivered to glasgow 8 Third technology run. Run 4Wafer to be identified and delivered to glasgow 9 Forth technology run. Run 5Wafer to be identified and delivered to glasgow 10 Forth technology run. Run 5Wafer to be identified and delivered to glasgow

LETI wafer thinning project flow Phase 2