Lect 4: Instruction Set and Addressing Modes. 386 Instruction Set (3.4)  Basic Instruction Set : 8086/8088 instruction set  Extended Instruction Set.

Slides:



Advertisements
Similar presentations
Register In computer architecture, a processor register is a small amount of storage available on the CPU whose contents can be accessed more quickly than.
Advertisements

Chapter 2 (cont.) An Introduction to the 80x86 Microprocessor Family Objectives: The different addressing modes and instruction types available The usefulness.
COMP 2003: Assembly Language and Digital Logic
ENGS 116 Lecture 41 Instruction Set Design Part II Introduction to Pipelining Vincent H. Berk September 28, 2005 Reading for today: Chapter 2.1 – 2.12,
1/2002JNM1 AL 00 Immediate Addressing Mode Mov AL, 3CH AL 3C.
Chapter 3 Addressing Modes
Chapter Four–80x86 Instruction Set Principles of Microcomputers 2015年5月17日 2015年5月17日 2015年5月17日 2015年5月17日 2015年5月17日 2015年5月17日 1 Chapter four 80x86.
6-1 ECE 424 Design of Microprocessor-Based Systems Haibo Wang ECE Department Southern Illinois University Carbondale, IL Intel 8088 Addressing modes.
Lect 3: Instruction Set and Addressing Modes. 386 Instruction Set (3.4) –Basic Instruction Set : 8086/8088 instruction set –Extended Instruction Set :
Azir ALIU 1 What is an assembly language?. Azir ALIU 2 Inside the CPU.
Handout 2 Digital System Engineering (EE-390)
Stack Memory H H FFFFF H FFFFE H SS 0105 SP 0008 TOS BOS BOS = FFFF = 1104F H H 1104F H.
Addressing modes – 1 The way in which an operand is specified is called the Address Mode.
The 8086 Assembly Programming Data Allocation & Addressing Modes
Addressing Modes Instruction – Op-code – Operand Addressing mode indicates a way of locating data or operands. – Any instruction may belong to one or more.
Operating Systems: Segments 1 Segmentation Hardware Support single user program system: – wish somehow to relocate address 0 to after operating system.
© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Chapter 2 The Microprocessor and its Architecture.
Assembly Language Advantages 1. It reveals the secret of your computer’s hardware and software. 2. Speed. 3. Some special applications and occasions. Disadvantages.
ICS312 Set 3 Pentium Registers. Intel 8086 Family of Microprocessors All of the Intel chips from the 8086 to the latest pentium, have similar architectures.
Microprocessor Systems Design I
Microprocessor Systems Design I Instructor: Dr. Michael Geiger Spring 2013 Lecture 4: 80386DX memory, addressing.
Microprocessor Systems Design I Instructor: Dr. Michael Geiger Spring 2014 Lecture 4: x86 memory.
© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Chapter 2 The Microprocessor and its Architecture.
Chapter 3: Addressing Modes. Copyright ©2009 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. The Intel Microprocessors:
CEG 320/520: Computer Organization and Assembly Language ProgrammingIntel Assembly 1 Intel IA-32 vs Motorola
CDP ECE Spring 2000 ECE 291 Spring 2000 Lecture 7: More on Addressing Modes, Structures, and Stack Constantine D. Polychronopoulos Professor, ECE.
1/2002JNM1 Positional Notation (Hex Digits). 1/2002JNM2 Problem The 8086 has a 20-bit address bus. Therefore, it can access 1,048,576 bytes of memory.
Low Level Programming Lecturer: Duncan Smeed Overview of IA-32 Part 1.
INSTRUCTION SET AND ASSEMBLY LANGUAGE PROGRAMMING
ECE291 Computer Engineering II Lecture 3 Josh Potts University of Illinois at Urbana- Champaign.
(-133)*33+44* *33+44*14 Input device memory calculator Output device controller Control bus data bus memory.
Chapter 2 Parts of a Computer System. 2.1 PC Hardware: Memory.
Carnegie Mellon 1 Machine-Level Programming I: Basics Lecture, Feb. 21, 2013 These slides are from website which accompanies the.
ECE291 Computer Engineering II Lecture 3 Josh Potts University of Illinois at Urbana- Champaign.
ECE291 Computer Engineering II Lecture 3 Dr. Zbigniew Kalbarczyk University of Illinois at Urbana- Champaign.
INTRODUCTION TO INTEL X-86 FAMILY
Addressing Modes. Addressing Mode The data is referred as operand. The operands may be contained in registers, memory or I/O ports, within the instruction.
MOV Instruction MOV destination,source  MOV AX,BX  MOV SUM,EAX  MOV EDX,ARRAY[EBX][ESI]  MOV CL,5  MOV DL,[BX]
Assembly Language Data Movement Instructions. MOV Instruction Move source operand to destination mov destination, source The source and destination are.
Microprocessor, Programming & Interfacing Tutorial 2- Module 3.
Microprocessors CSE- 341 Dr. Jia Uddin Assistant Professor, CSE, BRAC University Dr. Jia Uddin, CSE, BRAC University.
Intel MP Organization. Registers - storage locations found inside the processor for temporary storage of data 1- Data Registers (16-bit) AX, BX, CX, DX.
Addressing Modes Instruction – Op-code – Operand Addressing mode indicates a way of locating data or operands. – Any instruction may belong to one or more.
Microprocessors CSE- 341 Dr. Jia Uddin Assistant Professor, CSE, BRAC University Dr. Jia Uddin, CSE, BRAC University.
Computer Science 516 Intel x86 Overview. Intel x86 Family Eight-bit 8080, 8085 – 1970s 16-bit 8086 – was internally 16 bits, externally 8 bits.
Microprocessor Systems Design I
Microprocessor Systems Design I
Introduction to 8086 Microprocessor
COURSE OUTCOMES OF MICROPROCESSOR AND PROGRAMMING
16.317: Microprocessor System Design I
ADDRESSING MODES.
16.317: Microprocessor System Design I
Microprocessor Systems Design I
Chapter 4 Data Movement Instructions
Assembly IA-32.
ADDRESSING MODES.
Assembly Lang. – Intel 8086 Addressing modes – 1
Basic of Computer Organization
BIC 10503: COMPUTER ARCHITECTURE
Data Addressing Modes • MOV AX,BX; This instruction transfers the word contents of the source-register(BX) into the destination register(AX). • The source.
8086 Registers Module M14.2 Sections 9.2, 10.1.
32-bit instruction mode(80386-Pentium 4 only)
CS 301 Fall 2002 Computer Organization
Chapter 3: Addressing Modes
The Microprocessor & Its Architecture
CNET 315 Microprocessor & Assembly Language
Computer Architecture CST 250
Addressing Modes MOV AX,BX Destination Source Data-Addressing Modes.
Data Movement Instructions
Unit-I 80386DX Architecture
Presentation transcript:

Lect 4: Instruction Set and Addressing Modes

386 Instruction Set (3.4)  Basic Instruction Set : 8086/8088 instruction set  Extended Instruction Set : 80286; several new instructions and additional addressing modes  specific instruction set:  See page 62, Fig 3.6 Addressing Modes of 386DX (3.5)  Addressing Modes: a method of specifying an operand Operands : in REG, Memory, I/O ports, and within Instruction  * Control Transfer : direct, indirect addressing  the modes available register addressing : REG immediate addressing: within Instruction direct addressing register indirect addressing based addressing indexed addressing based indexed addressing MEM or I/O

Addressing Modes  Register Operand Addressing Mode can be accessed in byte, word, or double word sizes. MOV AX, BX Byte: AL, AH, BL, BH, CL, CH, DL, DH Word: AX, BX, CX, DX, SP, BP, SI, DI, CS, DS, SS, ES, FS, GS Double Word: EAX, EBX, ECX, EDX, ESP, EBP, ESI, EDI See Fig 3.8 in page 64  Immediate Operand Addressing an operand is part of the instruction MOVAL, 15H 8 bits, 16 bits, and 32 bits in length See Fig 3.10 in page bit Memory Operand Addressing Modes  16-bit addressing modes and 32-bit addressing modes  Physical address = Segment Base: EA(effective address) Segment Base Address(SBA) : the starting location of the segment EA : the offset of the operand from the beginning of the segment of memory EA = Base + Index + Displacement Base = BX or BP, Index = SI or DI, displacement = 8-bit or 16-bit

16-bit Memory Operand Addressing  Direct Addressing Mode PA = Segment Base : Direct Address MOV CX, [1234H] See fig 3.13 MOV CX, [1234H] IP CS DS SS ES FS GS AX BX CX DX SP BP SI DI B 0E XX XXXX ED BE BEED

16-bit Memory Operand Addressing  Register Indirect Addressing Mode PA = Segment Base : Indirect Address {BX,BP,SI,DI} example : MOVAX, [SI] MOV AX,[SI] IP CS DS SS ES FS GS AX BX CX DX SP BP SI DI B 04 XX XXXX ED BE BEED 1234

16-bit Memory Operand Addressing  Based Addressing Mode PA = Segment Base : {BX or BP} + {8-bit or 16-bit displacement} Base register : the beginning of a data structure See Fig 3.16 (b) in page 74 Example: MOV [BX]+1234H, AL MOV [BX]+1234H, AL IP CS DS SS ES FS GS AX BX CX DX SP BP SI DI XX ED 1000 Displacement Base Register + Element 0 Element 1 Data Structure Element n-1

16-bit Memory Operand Addressing  Indexed Addressing Mode PA = Segment Base : {SI, DI}+{8-bit or 16-bit displacement} Displacement : the starting address of an array; Index: selects the specific element in the array Example: MOVAL, [SI]+2000H Index Register Displacement + Element 0 Element 1 Array of data Element n-1 IP CS DS SS ES FS GS AX BX CX DX SP BP SI DI A XX XX 1000 MOV AL, [SI]+1234H BE

16-bit Memory Operand Addressing  Based-Indexed Addressing Mode PA= Seg Base: {BX, BP}+{SI,DI}+{8-bit or 16-bit displacement} to access complex data structures See fig 3.20 in page 80 Example: MOVAH, [BX][SI]+1234H opcode : 8A

32-bit Memory Operand Addressing Modes  Enhanced in two ways Scale factor : EA = base + (index x scale factor) + displacement PA = Segment Base: EA See fig 3.23 in page 83: change 16-bit displacement to 32-bit displacement How can we specify the 32-bit extension modes? –Default (D) bit in the code segment descriptor –2 prefixes to the instruction set Operand size prefix Address size prefix