ICS312 Set 3 Pentium Registers. Intel 8086 Family of Microprocessors All of the Intel chips from the 8086 to the latest pentium, have similar architectures.
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Presentation on theme: "ICS312 Set 3 Pentium Registers. Intel 8086 Family of Microprocessors All of the Intel chips from the 8086 to the latest pentium, have similar architectures."— Presentation transcript:
Intel 8086 Family of Microprocessors All of the Intel chips from the 8086 to the latest pentium, have similar architectures and use the same core assembly language.
REGISTERS AVAILABLE TO ASSEMBLER PROGRAMMER General registers Pointer and Index Registers Flags register Segment registers
The registers are 8-bit, 16-bit, or 32-bit, high- speed storage locations inside the CPU which can be accessed through the CPU's internal data bus much more quickly than data stored in external memory.
General Purpose or Data Registers The general purpose registers are used for arithmetic operations and moving data Register Name Upper Half Lower Half Name and Special Functions (besides arithmetic): EAX AX Accumulator Used for I/O no name AHAL EBX BX Base Register Used for indirectly addressing items in the data segment no name BHBL ECX CX Count Register Used for counting CHCL EDX DX Data Register DHDL
Pointer and Index Registers o These are used to hold the offset addresses of data and instructions. o Offset addresses refers to the distance of a variable, label, or instruction from the beginning of its segment O Can also be used for arithmetic and moving data Register Name Abbreviation Function Destination Index EDI (32 bit) or DI (16 bit) Index into data segment, but for the string instructions it’s the index into segment ES Source Index ESI or SI Index into data segment Base Pointer EBP or BP 2 nd Index into stack Stack Pointer ESP or SP Indexes top of stack
Flags Register (EFLAGS or FLAGS) o Individual bits in the FLAGS register give information about the status of the processor. o The use of flags will be discussed further later. o Status flags - reflect the results of instructions (add, subtract, multiply, divide) executed by the processor. o Frequently used flags Zero flag (ZF) Sign flag (SF) Carry flag (CF) Overflow Flag (OF)
Segment Registers 16-bit registers that hold the base locations(base addresses) for program instructions, data, and the stack Register Name Abbreviation The function of the segment whose starting address is encoded in the segment register involved Code Segment CS Holds program code Data Segment DS Holds program data Extra Segments ES, FS, GS Also used for data Stack Segment SS Holds program stack
Memory Segments o Memory segments contain 2 16 (64K) consecutive memory addresses o Each segment has a 16 bit segment number (0-FFFFh) which is placed in a associated segment register o Within a segment a memory address is specified by a 16-bit offset (0-FFFFh) which indicates the number of bytes from the beginning of the segment
Memory Address Logical memory addresses are given in SEGMENT:OFFSET form. Examples: 0FF0Eh:0010h CS:IP DS:SI ES:DI SS:SP Physical (absolute) memory addresses are calculated using the formula: Physical Address = 10h * SEGMENT + OFFSET Example: Logical Address (using hex nos.): 0FF0E:0010 Physical Address: 0FF0E0 + 0010 = 0FFF00 Note. Logical Addresses are not unique. e.g. 0FF0E:0010 = 0FF0D:0020
Instruction Pointer (EIP or IP) o Gives the offset address (in the code segment) for the next instruction to be executed. o The IP cannot be used as the operand of any instruction.
Textbook Reading (Jones): Read chapter 2, which provides an Assembler overview