1. Computer Science 516 Intel x86 Overview

2. Intel x86 Family Eight-bit 8080, 8085 – 1970s 16-bit 8086 – 1979 8088 was internally 16 bits, externally 8 bits 80286 – 1982 – 24-bit addressing extensions 80386 – 1985 – 32-bit architecture Retained 16-bit compatibility X64 – 1999 – 64-bit architecture AMD initially proposed

3. 8086 Registers Main Registers Used for arithmetic, genereal purpose Segment Registers Used for addressing Other Registers Many added since original design Not always well documented Control, debugging, et cetera

4. 8086 Main Registers All 16-bit, comprising high and low 8-bit registers AX (AH, AL) BX (BH, BL) CX (CH, CL) DX (DH, DL) Other registers SP - Stack Pointer BP - Base Pointer SI - Source Index DI - Destination Index

5. 8086 Segment registers CS - Code Segment DS - Data Segment SS - Stack Segment ES - Extra Segment Other: IP - instruction pointer

6. 8086 Addressing 1 megabyte address space 20 bits needed for addressing Only 16 bits in 8086 regisers Solution: shift segment bit left 4 bits Sum provided 20-bit address

7. 8086 Address Example Data Segment - 1000 Data offset - 0040 Add: 1 0 0 0 0 0 0 4 0 Get: 1 0 0 4 0

8. Registers In x86 Extensions 32-bit Add 'E' in front of register name, e.g. EAX Old names still usable for low-order part of registers Added two new segment registers, FS and GS 64-Bit Add 'R' in front of register name, e.g. RAX Old names still usable Eight additional general purpose registers (R8-R15)

9. Floating Point Performed in Co-processor Separate chip (8087, 80287, 80387) Eight 80-bit registers Integrated with main processor since 486

10. Vector Extensions MMX AVX SSE (multiple variations) 128-bit (X), 256-bit (Y), 512-bit (Z) formats Up to 32 registers XMM00 through ZMM31 Lower precision names still usable

11. IA64 Instruction Format From the Intel architecture manual, volume 2:

12. IA64 Instruction Prefixes Four Groups Lock and Repeat Prefixes Segment Override Prefixes, Branch Hints, Bounds Operand Size Override Prefix 16 vs. 32-bit operations Address Size Override Prefix 16 vs. 32-bit addresses

13. IA64 Opcodes 1, 2, or 3-byte opcodes Opcodes may also require part of Mod R/M field Instruction decoding fairly complex See Appendix A in Volume 2 of Intel® 64 and IA-32 Architectures Software Developer’s Manual

14. IA64 Mod R/M Field Mod and r/m fields form 32 possible values: eight registers 24 addressing modes. Register/opcode field specifies: a register number, or three more bits of opcode information Purpose depends upon primary opcode See Tables 2-1 and 2-2 in Software Developers Guide

15. IA64 SIB Scale: 1, 2, 4, 8 butes Index register number Base register number SeeTable 2-3 in Volume 2 of Software Developers Guide

16. IA64 Displacement Added to some Base address Base address can be in a segment register Base address can be in another register Some restrictions on code segment base

17. IA64 Immediate Data Immediate data = data in instruction No additional memory access required Varying lengths (8, 16 bits) 32 bits allowed with later instructions

18. Some 64-bit Changes REX Prefix In addition to other prefixes, identifies use of additional registers Displacement and Immediate data May be 8 or 32 bits in length Sign extended to 64 bits

19. 32 and 64-bit Segment Registers 32-bit and 64-bit segment format: Original segment held part of an address Now holds index into a table of descriptor values Local or Global Descriptor Table RPL = Requested Privilege level (Read/Write, read/Execute) More info: http://www.cs.cmu.edu/~410/doc/segments/segments.html

20. More to come…