Jai Henwood Introduction to VHDL ECE /24/03 Dr. Veton Këpuska

Goals and Objectives - The goal of my project was to further my knowledge of VHDL - Provide some history of the development of VHDL - Introduce VHDL syntax and a few key concepts about VHDL.

Overview History of VHDL Go through a few example of VHDL: - 8 bit shifter - 4 to 1 Mux - State machine

VHDL VHDL is an International IEEE Standard Specification Language (IEEE ) for Describing Digital Hardware Used by Industry Worldwide VHDL stands for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language

History of VHDL In the 1970’s the initial idea for a Hardware Description Language was discussed. But, the VHSIC program wasn’t launched until The goal was to create a common language that would shorten the time from concept to implementation for hardware design.

History of VHDL In July 1983 the contract was awarded to create VHDL by the Department of Defense - Intermetrics - IBM - Texas Instruments August 1985 Version 7.2 was released

History of VHDL It was first in December of 1987 that IEEE standardized VHDL VHDL also became an ANSI standard in 1988 In September of 1993 VHDL was re- standardized to clarify and enhance the language

History of VHDL In 1998 a committee convened to update the VHDL-1993 standard. In 2001 IEEE revised the 1993 standard and the new standard today is

Other Languages besides VHDL On the way to standardizing VHDL other languages were devolved and some are still used AHPL A Hardware Programming Language CDL computer design Language CONLAN CONsensus LANguage

Other Languages besides VHDL IDL Interactive Design Language ISPS Instruction Set Processor Specification TEGAS Test Generation And Simulation TI-HDL TI Hardware Description Language Verilog Gateway Design Automation: 1985 ZEUS A HDL by GE cooperation

Basic VHDL Terms Entity - All designs are expressed in terms of entities. An entity is the most basic building block in a design. The uppermost level of the design is the top-level entity. If the design is hierarchical, then the top-level description will have lower-level descriptions contained in it. These lower-level descriptions will be lower-level entities contained in the top- level entity description. Architecture - All entities that can be simulated have an architecture description. The architecture describes the behavior of the entity. A single entity can have multiple architectures. One architecture might be behavioral, while another might be a structural description of the design. Configuration - A configuration statement is used to bind a component instance to an entity-architecture pair. A configuration can be considered as a parts list for a design. It describes which behavior to use for each entity, much like a parts list describes which part to use for each part in the design.

4 to 1 MUX Mux Sel InputsOutputs ABCDABCD Q

4 to 1 MUX library ieee; use ieee.std_logic_1164.all; -- 4 to 1 mux entity mymux is port (A, B, C, D : in std_logic_vector(0 to 3); Sel : in std_logic_vector ( 0 to 1 ); Q : out std_logic_vector(0 to 3) ); end mymux; Library you need to include Comment entity “name_of_entity” is port(all your input and output signals); end “name_of_entity”;

4 to 1 MUX architecture mux4 of mymux is constant delay : time := 100 ns; begin mux_proc : process ( A, B, C, D, Sel ) variable temp : std_logic_vector(0 to 3); begin case Sel is when "00" => temp := A; when "01" => temp := B; when "10" => temp := C; when "11" => temp := D; when others => temp := "XXXX"; end case; Q <= temp after delay; end process mux_proc; end mux4; mux4 is the name of my architecture Declaration of time as a constant begin the architecture Process mux_proc is initialized Variable temp is declared begin process mux_proc case on the Sel singal If anything else then temp is don’t care If there was a delay on the mux end process end architecture

TestBench for 4 to 1 MUX library ieee; use ieee.std_logic_1164.all; entity mux_testbench is end mux_testbench; architecture test of mux_testbench is signalA : std_logic_vector(0 to 3); signal B: std_logic_vector(0 to 3); signal C: std_logic_vector(0 to 3); signalD: std_logic_vector(0 to 3); signalSel: std_logic_vector(0 to 1); signal Q: std_logic_vector(0 to 3); still have to begin with entity end the entity test is the name of the architecture the signals have to be the same as the port signals in your entity declaration of the program you want to test.

TestBench for 4 to 1 MUX component mymux is port (A, B, C, D : in std_logic_vector(0to3); Sel : in std_logic_vector ( 0 to 1 ); Q : out std_logic_vector(0 to 3)); end component; begin test_mux: mymux port map(A => A, B => B, C => C, D => D, Sel => Sel, Q => Q ); This component declaration tells us that we have 5 inputs A,B,C,D and Sel; we also have one output Q The port map is used to link the signal A from your VHDL program to the signal A in your testbench Used incase you want to use different names

TestBench for 4 to 1 MUX test_process: process beginA<="1010"; B<="1011"; C<="1100"; D<="1101"; Sel<="00"; wait for 500 ns; Sel<="01"; wait for 500 ns; Sel<="10"; wait for 500 ns; Sel<="11"; wait for 500 ns; end process; end test; initialize your signal when Sel is 00 it should let A come through on Q with a delay of 100ns when Sel is 01 Q should be B end the process test_process end the test

8- Bit Shifter Shifter clk rst load data 8 bits Q Input Output

8 – Bit Shifter -- 8-Bit Shift Register library ieee; use ieee.std_logic_1164.all; entity shift is port (CLK, RST, LOAD : in bit; Data : in bit_vector(0 to 7); Q : out bit_vector(0 to 7)); end rotate; Comment Library you need to include entity “name_of_entity” is port(all your input and output signals); end “name_of_entity”;

8 – bit shifter architecture shifter1 of shift is begin reg : process(RST, CLK) variable reg : bit_vector(0 to 7); begin if(RST = '1') then reg := " "; elsif(CLK = '1' and CLK'event) then if(LOAD = '1') then reg := Data;. else reg := reg(1 to 7) & reg(0); end if; Q <= reg; end process; end shifter1; shifter1 is the name of my architecture shift is the name of my entity reg is the name of my process reg is also a local variable Begin the process reg if RST clear reg else wait for a clock event then reg = Data if LOAD signal is high a bit shift R gets the value of reg end process end architecture

TestBench for 8 bit shifter library ieee; use ieee.std_logic_1164.all; entity shift_testbench is end shift_testbench; architecture test of shift_testbench is Signal CLK: bit; signal RST: bit; signal LOAD : bit; signal Data :bit_vector(0 to 7); signal Q :bit_vector(0 to 7); still have to begin with entity end the entity test is the name of the architecture the signals have to be the same as the port signals in your entity declaration of the program you want to test.

TestBench for 8 bit Shifter component shift is port (CLK, RST, LOAD : in bit; Data : in bit_vector(0 to 7); Q : out bit_vector(0 to 7)); end component; begin test_shift: shift port map( CLK => CLK, RST => RST, LOAD => LOAD, Data => Data, Q => Q); port has all the input and output signals used in the VHDL program The port map is used to link the signal Data from your VHDL program to the signal Data in your testbench

TestBench for 8 bit Shifter clock_gen : process begin clk <= '0', '1' after 50 ns; wait for 100 ns; end process; RST<='1', '0' after 200 ns; test_process: process begin Data<=" "; LOAD<='1', '0' after 400 ns wait; end process; end test; creates a clock signal this is a 10 MHz clock end the process clock_gen this is only done once to set it off data is give a value every 400 ns Data is reset to “ ” end the process test_process end the test

System Overview Programmable Logic Device DIP Switches Strobe (pushbutton) An open switch will have a value of ‘1’ and closed switch value of ‘0’ LED

PLD monitors data stream looking for commands PLD responds to On command by turning LED On PLD responds to Off command by turning LED Off Functional Overview On Off “AB”“50”

Details PLD receives 4 bits (one Hex digit) of data at a time Data is ready on rising edge of Strobe Output ‘1’ to LED for ON / ‘0’ for OFF

Programs Used To enter VHDL text nedit To compilencvhdl made by Cadence To elaboratencelab made by Cadence To simulatencsim made by Cadence To create html and state diagrams visual_elite made by Innoveda

Why use VHDL Compared to schematic diagrams - More standardized & portable - Easier to create - More concise - Easier to comment - Easier to read - Faster to simulate schematics/layouts can be automatically generated from VHDL by logic synthesis

Reasons for Modeling requirements specification documentation testing using simulation formal verification synthesis