1 Comparators: Procedures Discussion D9.2 Example 22.

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Presentation transcript:

1 Comparators: Procedures Discussion D9.2 Example 22

2 A 1-Bit Comparator The variable Gout is 1 if x > y or if x = y and Gin = 1. The variable Eout is 1 if x = y and Gin = 0 and Lin = 0. The variable Lout is 1 if x < y or if x = y and Lin = 1.

3 The variable Gout is 1 if x > y or if x = y and Gin = 1. The variable Eout is 1 if x = y and Gin = 0 and Lin = 0. The variable Lout is 1 if x < y or if x = y and Lin = 1.

4 Gout = x * y' + x * Gin + y' * Gin Eout = x' * y' * Gin' * Lin' + x * y * Gin' * Lin' Lout = x' * y + x' * Lin + y * Lin

5 A 4-Bit Comparator

6 4-Bit Comparator Using a VHDL Procedure -- Example 22a: 4-bit comparator using a procedure library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity comp4a is port( x : in STD_LOGIC_VECTOR(3 downto 0); y : in STD_LOGIC_VECTOR(3 downto 0); gt : out STD_LOGIC; eq : out STD_LOGIC; lt : out STD_LOGIC ); end comp4a;

7 architecture comp4a of comp4a is procedure comp1bit( x: in std_logic; y: in std_logic; Gin: in std_logic; Lin: in std_logic; Gout: out std_logic; Lout: out std_logic; Eout: out std_logic) is begin Gout := (x and not y) or (x and Gin) or (not y and Gin); Eout := (not x and not y and not Gin and not Lin) or (x and y and not Gin and not Lin); Lout := (not x and y) or (not x and Lin) or (y and Lin); end procedure; Procedures

8 begin process(x,y) variable G, L, E: STD_LOGIC_VECTOR(4 downto 0); begin G(0) := '0'; L(0) := '0'; for i in 0 to 3 loop comp1bit(x(i),y(i),G(i),L(i),G(i+1),L(i+1),E(i+1)); end loop; gt <= G(4); eq <= E(4); lt <= L(4); end process; end comp4a;

9 Simulation of comp4a.vhd

10 4-Bit Comparator Using Relational Operators Relational and Logical Operators

11 -- Example 22b: 4-bit comparator -- using relational operators library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity comp4b is port( x : in STD_LOGIC_VECTOR(3 downto 0); y : in STD_LOGIC_VECTOR(3 downto 0); gt : out STD_LOGIC; eq : out STD_LOGIC; lt : out STD_LOGIC ); end comp4b;

12 architecture comp4b of comp4b is begin process(x,y) begin gt <= '0'; eq <= '0'; lt <= '0'; if x > y then gt <= '1'; end if; if x = y then eq <= '1'; end if; if x < y then lt <= '1'; end if; end process; end comp4b;

13 Simulation of comp4b.vhd

14 Comparators XNOR X Y Z Z = X xnor Y Z = Y) Recall that an XNOR gate can be used as an equality detector X Y Z if X = Y then Z <= '1'; else Z <= '0'; end if;

15 4-Bit Equality Comparator A: in STD_LOGIC_VECTOR(3 downto 0); B: in STD_LOGIC_VECTOR(3 downto 0); A_EQ_B: out STD_LOGIC;

16 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity eqdet4 is Port ( A : in std_logic_vector(3 downto 0); B : in std_logic_vector(3 downto 0); A_EQ_B : out std_logic); end eqdet4; architecture Behavioral of eqdet4 is signal C: std_logic_vector(3 downto 0); begin C <= A xnor B; A_EQ_B <= C0 and C1 and C2 and C3; end Behavioral;

17 Signed Comparators comp A(n-1:0) B(n-1:0) A_EQ_B A_GT_B A_LT_B A_UGT_B A_ULT_B A, B signed A, B unsigned Signed: 2's complement signed numbers

18 -- Comparator for unsigned and signed numbers library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity comp is generic(width:positive); port ( A: in STD_LOGIC_VECTOR(width-1 downto 0); B: in STD_LOGIC_VECTOR(width-1 downto 0); A_EQ_B: out STD_LOGIC; A_GT_B: out STD_LOGIC; A_LT_B: out STD_LOGIC; A_ULT_B: out STD_LOGIC; A_UGT_B: out STD_LOGIC ); end comp; comp A(n-1:0) B(n-1:0) A_EQ_B A_GT_B A_LT_B A_UGT_B A_ULT_B

19 architecture comp_arch of comp is begin CMP: process(A,B) variable AVS, BVS: signed(width-1 downto 0); begin for i in 0 to width-1 loop AVS(i) := A(i); BVS(i) := B(i); end loop; A_EQ_B <= '0'; A_GT_B <= '0'; A_LT_B <= '0'; A_ULT_B <= '0'; A_UGT_B <= '0'; if (A = B) then A_EQ_B <= '1'; end if; if (AVS > BVS) then A_GT_B <= '1'; end if; if (AVS < BVS) then A_LT_B <= '1'; end if; if (A > B) then A_UGT_B <= '1'; end if; if (A < B) then A_ULT_B <= '1'; end if; end process CMP; end comp_arch; comp A(n-1:0) B(n-1:0) A_EQ_B A_GT_B A_LT_B A_UGT_B A_ULT_B Note: All outputs must be assigned some value. The last signal assignment in a process is the value assigned

20 4-Bit Comparator