Built-In Self-Test of Programmable I/O Cells in Virtex-4 FPGAs Bradley F. Dutton, Lee W. Lerner, and Charles E. Stroud Dept. of Electrical & Computer Engineering Auburn University

B. Dutton 5/15/08North Atlantic Test Workshop2 Outline of Presentation  Previous Work  Overview of Virtex-4 I/O Tiles  Virtex-4 I/O BIST architecture  ILOGIC/OLOGIC (input/output logic)  SERDES (serialization/deserialization)  I/O Standards  Capabilities and Limitations  Conclusion

B. Dutton 5/15/08North Atlantic Test Workshop3 Previous Work in I/O BIST  I/O BIST for Atmel AT94K (NATW’06)  Proposed BIST architecture for 100% stuck-at fault  Configure bi-directional Cell Under Test (CUT)  23 BIST configurations to test all modes of operation  AT94K I/O Cells are simple compared to Virtex-4  2 Flip-Flops, 4 Multiplexors, 3 I/O standards =TPG =ORA I/O Cells Under Test

B. Dutton 5/15/08North Atlantic Test Workshop4 Virtex-4 I/O Tiles  Two I/O Cells form I/O Tile  Dedicated shift routing for SERDES data width expansion  Routing to support complementary differential I/O standards  All I/O Cells are identical  10 Flip-Flops  32 Multiplexors  69 I/O Standards More complicated than Atmel More complicated than Atmel Input/Output Buffer (I/O Buffer) Input/Output Buffer (I/O Buffer) To/from Device Resources Input Logic (ILOGIC) Output Logic (OLOGIC) From Device Resources To/From Device Resources Input Logic (ILOGIC) Output Logic (OLOGIC) From Device Resources I/O Cell BSCAN EXTEST Access

B. Dutton 5/15/08North Atlantic Test Workshop5 Virtex-4 I/O BIST Architecture  DSPs configured as counters to address 18 Kbit Block RAMs  Block RAMs store deterministic and pseudorandom test patterns  Greater controllability of test patterns  Multiple TPGs address alternating rows of BUTs  Bidirectional I/O buffers under test (BUTs) =ORA =TPG =BUT

B. Dutton 5/15/08North Atlantic Test Workshop6 Virtex-4 I/O BIST Architecture =ORA =TPG =BUT DSP BRAMs

B. Dutton 5/15/08North Atlantic Test Workshop7 ILOGIC/OLOGIC Fault Coverage  Can only test bi-directional buffer modes  Two undetected faults result

B. Dutton 5/15/08North Atlantic Test Workshop8 SERDES Overview O Q1 Q2 Q3 Q4 Q5 Q6 ISERDES D D1 D2 D3 D4 D5 D6 OSERDES Q T1 T2 T3 T4 T CLK CLKDIV OCE REV SHIFTIN1 SHIFTIN2 SR TCE SHIFTOUT1 SHIFTOUT2 SHIFTIN1 SHIFTIN2 SHIFTOUT1 SHIFTOUT2 CLK CLKDIV BITSLIP CE1 CE2 DLYCE DLYINC DLYRST SR OCLK REV TO FPGA INTERNAL RESOURCES FROM FPGA INTERNAL RESOURCES Input Buffer Output Buffer PAD I/O Buffer FROM FPGA INTERNAL RESOURCES TO OTHER ISERDES IN I/O TILE TO OTHER OSERDES IN I/O TILE OSERDES: parallel to serial conversion ISERDES: serial to parallel conversion

B. Dutton 5/15/08North Atlantic Test Workshop9 SERDES BIST Configurations  SERDES requires more TPG and ORA lines  Solution: Block RAMs configured as 512x36bit Reduces total test vector count to 512 Reduces total test vector count to 512  7 outputs per ISERDES require 7 ORAs  Data serialization/deserialization requires high speed clock  Solution: instantiate clock divide circuitry and use the divided clock for TPGs and ORAs  Amount of clock division depends on the data width  Deserialized data must be identically aligned on ISERDES parallel outputs  Solution: add a training pattern to vector set and a Bitslip synchronizer circuit

B. Dutton 5/15/08North Atlantic Test Workshop10 SERDES BIST Configurations  Bitslip operation reorders deserialized data on inputs  Bitslip synchronizer circuit aligns deserialized data prior to BIST  Synchronizer EN line enables/disables circuit D Q CLR D Q D Q X Y Z To ISERDES ISERDES Q2 CLKDIV Synchronizer Enable from TPG TPG Bitslip Clock Cycle Init ISERDES Q X FF X Y FF X Z FF BITSLIP

B. Dutton 5/15/08North Atlantic Test Workshop11 I/O Standards  I/O Standards are tested with ILOGIC/OLOGIC architecture  69 I/O standards, 9 are not bidirectional  Four classes of I/O standards  Single ended with Vref require an external reference voltage supplied to one I/O buffer per 16 I/O  DCI requires two external reference resistors in each I/O bank (64 I/O)  Complementary differential requires some modification of the template architecture SourceLinesDestination a) single ended Input Buffer Output Buffer c) complementary differential (requires two I/O cells) Differential Input Buffer Output Buffer i Output Buffer j d) digitally controlled impedance (DCI) (single or split termination at source, destination, or both) V REF Differential Input Buffer Output Buffer b) single ended requiring V REF (1 V REF per 16 I/O buffers) Input Buffer z R Output Buffer R R V CCO R

B. Dutton 5/15/08North Atlantic Test Workshop12 BIST Configuration Summary I/OBISTArchitecture # of BISTConfigurations Total BIST Clock Cycles Clock Cycles(constant) Total Download Size (Kbits)* Size (Kbits)* (varies w/ size) ILOGIC/OLOGIC881924,034 SERDES819,12410,384 I/O Standards ,828 TOTAL7827,81220,246 * Configuration file size for SX35 using compressed configuration files and partial reconfiguration files  I/O Standards configurations  Less than 30% of configuration bits  Less than 2% of BIST clock cycles  78 configurations, but smaller than 6 full downloads  Total test time = 405 msec for SX35

B. Dutton 5/15/08North Atlantic Test Workshop13 Virtex-4 I/O BIST Configuraiton Generation Programs  Three XDL template file generation programs  V4iobist – ILOGIC, OLOGIC, I/O buffer logic resources  V4iobistios – SERDES logic resources  V4iobistd – complementary differential I/O standards  Three XDL modification programs  V4iobmod - ILOGIC, OLOGIC, I/O buffer logic resources  V4iobmodios – SERDES logic resources  V4iobrmod – I/O standards

B. Dutton 5/15/08North Atlantic Test Workshop14 BIST Configuration Generation Process BIST Programs BitGen.exe BIT file XDL file NCD file XDL.exe download FPGA Editor verification on FPGA  XDL: Xilinx Description Language  Can generate configurations for every Virtex-4 device in any package  FX12 not currently supported due to only 1 column of BRAMs in Power PC rows

B. Dutton 5/15/08North Atlantic Test Workshop15 All I/O Buffers Under Test in Virtex-4 FX20 as viewed in Xilinx FPGA Editor BRAMs for TPGs I/O tiles under test and corresponding ORAs DSPs for TPGs

B. Dutton 5/15/08North Atlantic Test Workshop16 Summary  3 architectures in 78 configurations to test I/O cells in every mode of operation  ILOGIC/OLOGIC  ISERDES/OSERDES  I/O Standards  Tests both bonded and unbonded I/O cells  Can be used for manufacturing or system level testing  Connecting devices should be tri-stated  Allows for testing at system frequencies