04/02/02EECS 3121 Lecture 23: DRAM + Driving large capacitances EECS 312 Reading: 10.3.3, 8.2.3, 8.5 (text)

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04/02/02EECS 3121 Lecture 23: DRAM + Driving large capacitances EECS 312 Reading: , 8.2.3, 8.5 (text)

04/02/02EECS 3122 Lecture Overview Midterm 2 review Finish discussion of memories Chip packaging overview Driving large loads

04/02/02EECS 3123 Midterm 2

04/02/02EECS 3124 Packaging

04/02/02EECS 3125 Bonding Techniques

04/02/02EECS 3126 Flip-Chip Bonding

04/02/02EECS 3127 Package Types

04/02/02EECS 3128 Package Parameters

04/02/02EECS 3129 Driving Large Capacitances

04/02/02EECS Using Cascaded Buffers This ignores self-loading (junction capacitance of driving stage): derivation on page 450 of text X = CL/Cin u = tapering factor

04/02/02EECS t p as a function of u and x

04/02/02EECS Impact of Cascading Buffers

04/02/02EECS Output Driver Design

04/02/02EECS How to Design Large Transistors We don’t want a long poly run – resistive and large parasitics Place multiple narrower devices in parallel (with same gate signal)

04/02/02EECS Tristate Buffers Useful for signals with multiple drivers 2 nd implementation is better in some cases b/c no series connected devices in output stage

04/02/02EECS Lecture Summary Chips must be put in a package to interface with other devices Sending signals off-chip requires a lot of driving capability Driving large loads is best done using cascaded buffers with tapering factor of e