ECE C03 Lecture 51 Lecture 5 Combinational Logic Implementation Using Multiplexers, ROMS, FPGAs Prith Banerjee ECE C03 Advanced Digital Logic Design Spring 1998

ECE C03 Lecture 52 Outline Combinational Logic Implementations Multiplexers Decoders ROMS Field Programmable Logic Arrays READING: Katz 4.2.2, 4.2.3, 4.2.4, 4.2.5, 10.3, Dewey 5.7

ECE C03 Lecture 53 Use of Multiplexers/Selectors Multi-point connections MUX DEMUX A B Sum A0A1B0 B1 SaSb Ss S0S1 Multiple input sources Multiple output destinations

ECE C03 Lecture 54 I I A Z A 0 1 Z I 0 I 1 General Concept of Using Multiplexers 2 data inputs, n control inputs, 1 output used to connect 2 points to a single point control signal pattern form binary index of input connected to output n n Two alternative forms for a 2:1 Mux Truth Table Z = A' I + A I 01 Functional form Logical form

ECE C03 Lecture 55 Use of Multiplexers/Selectors Z = A' I + A I 01 Z = A' B' I0 + A' B I1 + A B' I2 + A B I3 Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 + A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7 In general, Z =  m I 2 -1 n k=0kk in minterm shorthand form for a 2 :1 Mux n 2:1 mux I 0 I 1 A Z I 0 A I 1 I 2 I 3 B Z 4:1 mux I 0 A I 1 I 2 I 3 B Z 8:1 mux C I 4 I 5 I 6 I 7

ECE C03 Lecture 56 Alternative Implementation Gate Level Implementation of 4:1 Mux Gate Level Implementation of 4:1 Mux Transmission Gate Implementation of 4:1 Mux Transmission Gate Implementation of 4:1 Mux thirty six transistors twenty transistors I3 I0 I2 I1 A B Z

ECE C03 Lecture 57 Design of Large Multiplexers Large multiplexers can be implemented by cascaded smaller ones Control signals B and C simultaneously choose one of I0-I3 and I4-I7 Control signal A chooses which of the upper or lower MUX's output to gate to Z 0 1 S 0 1 S 0 1 S 0 1 S 0 1 S1 2 3 S0 C AB I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 C C C Z Alternative 8:1 Mux Implementation 4:1 mux 4:1 mux 8:1 mux 2:1 mux S S 1 S 0 S 1 S 0 Z ACB I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 0 1

ECE C03 Lecture 58 Multiplexers/Selectors as General Purpose Blocks 2 :1 multiplexer can implement any function of n variables n-1 control variables; remaining variable is a data input to the mux n-1 Example: F(A,B,C) = m0 + m2 + m6 + m7 = A' B' C' + A' B C' + A B C' + A B C = A' B' (C') + A' B (C') + A B' (0) + A B (1) 8:1 MUX S2 S1 S0 ABC F "Lookup Table" S1 S0 AB 4:1 MUX C C 0 1 F A B C F C C 0 1

ECE C03 Lecture 59 I I n 0 1 I n … FI 2 I n 0 1 … Generalization of Multiplexer/Selector Logic n-1 Mux control variables single Mux data variable Four possible configurations of the truth table rows Can be expressed as a function of In, 0, 1 Example: G(A,B,C,D) can be implemented by an 8:1 MUX: K-map Choose A,B,C as control variables Multiplexer Implementation TTL package efficient May be gate inefficient TTL package efficient May be gate inefficient G 8:1 mux ABC S 2 S 1 S 0 1 D 0 1 D D D D

ECE C03 Lecture 510 Decoders/Demultiplexers Decoder: single data input, n control inputs, 2 outputs control inputs (called select S) represent Binary index of output to which the input is connected data input usually called "enable" (G) n 1:2 Decoder: O0 = G S; O1 = G S 2:4 Decoder: O0 = G S0 S1 O1 = G S0 S1 O2 = G S0 S1 O3 = G S0 S1 3:8 Decoder: O0 = G S0 S1 S2 O1 = G S0 S1 S2 O2 = G S0 S1 S2 O3 = G S0 S1 S2 O4 = G S0 S1 S2 O5 = G S0 S1 S2 O6 = G S0 S1 S2 O7 = G S0 S1 S2

ECE C03 Lecture 511 Alternative Implementations 1:2 Decoder, Active High Enable 1:2 Decoder, Active Low Enable 2:4 Decoder, Active High Enable 2:4 Decoder, Active Low Enable Output0 G Select Output1 Output0 /G Select Output1 Select0Select1 Output2 Output3 Output0 G Output1 Select0Select1 Output2 Output3 Output0 /G Output1

ECE C03 Lecture 512 Switch Level Implementations Select G Output 0 Select Output 1 Select "0" Select G Output 0 1 Naive, Incorrect Implementation All outputs not driven at all times Correct 1:2 Decoder Implementation

ECE C03 Lecture 513 Switch Implementation of 2:4 Decoder Operation of 2:4 Decoder S0 = 0, S1 = 0 one straight thru path three diagonal paths

ECE C03 Lecture 514 Decoder as a Logic Building Block Decoder Generates Appropriate Minterm based on Control Signals Example Function: F1 = A' B C' D + A' B' C D + A B C D F2 = A B C' D' + A B C F3 = (A' + B' + C' + D') 3:8 dec ABC Enb ABC S 2 S 1 S 0

ECE C03 Lecture 515 A B C D A A A A A A A A A A A A A A A F 1 F A S 3 S 2 S 1 S 0 4:16 dec Enb BCD F 2 Decoder as a Logic Building Block If active low enable, then use NAND gates!

ECE C03 Lecture 516 Alternative Implementation of 32:1 Mux Multiplexer Only Multiplexer + Decoder W Y S2 S1 S0 I7 F(A, B, C, D, E) I0 I15 I23 I31 I6 I5 I4 I3 I2 I1 A B C D E F(A, B, C, D, E)

ECE C03 Lecture 517 5:32 Decoder 5:32 Decoder Subsystem \EN S4 S3 S2 S1 S0... \Y31 \Y0 \EN S2 S1 S0 S2 S1 S0 S2 S1 S0 S2 S1 S0 \Y31 \Y30 \Y29 \Y28 \Y27 \Y26 \Y25 \Y24 \Y23 \Y22 \Y21 \Y20 \Y19 \Y18 \Y17 \Y16 \Y15 \Y14 \Y13 \Y12 \Y11 \Y10 \Y9 \Y8 \Y7 \Y6 \Y5 \Y4 \Y3 \Y2 \Y1 \Y0

ECE C03 Lecture 518 Read-Only Memories ROM: Two dimensional array of 1's and 0's Row is called a "word"; index is called an "address" Width of row is called bit-width or wordsize Address is input, selected word is output Dec 0n-1 Address 2 -1 n 0 +5V Word Line 0011 Word Line 1010 Bit Lines j i Internal Organization

ECE C03 Lecture 519 Implementing Logic with ROMs F0 = A' B' C + A B' C' + A B' C F1 = A' B' C + A' B C' + A B C F2 = A' B' C' + A' B' C + A B' C' F3 = A' B C + A B' C' + A B C' addressoutputs ROM 8 words ¥ 4 bits ABCF 0 F 1 F 2 F 3 B AddressWord Contents A C F F F F by

ECE C03 Lecture 520 ROMs vs PLAs Not unlike a PLA structure with a fully decoded AND array! Not unlike a PLA structure with a fully decoded AND array! ROM vs. PLA: ROM approach advantageous when (1) design time is short (no need to minimize output functions) (2) most input combinations are needed (e.g., code converters) (3) little sharing of product terms among output functions ROM problem: size doubles for each additional input, can't use don't cares PLA approach advantangeous when (1) design tool like espresso is available (2) there are relatively few unique minterm combinations (3) many minterms are shared among the output functions PAL problem: constrained fan-ins on OR planes Memoryarray 2 n words by m bits m output lines n address lines Decoder 2 n word lines

ECE C03 Lecture 521 Read-Only Memories 2764 EPROM 8K x 8 16K x 16 Subsystem 2764 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 O0 O1 O2 O3 O4 O5 O6 O7 OE CS PGM VPP A10 A11 A12 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 O0 O1 O2 O3 O4 O5 O6 O7 OE CS PGM VPP A10 A11 A12 D7:D0 D15:D8 U3 U2 U1 U0

ECE C03 Lecture 522 Combinational Design with FPGAs Programmable Logic Devices = PLD Field Programmable Gate Arrays = FPGAs Altera MAX Family Actel Programmable Gate Array Xilinx Logical Cell Array PALs, PLAs = Gate Equivalents (s) of Gate Equivalents!

ECE C03 Lecture 523 Clk MUX Output MUX Q F/B MUX Invert Control AND ARRAY CLK pad Altera Erasable Programmable Logic Devices Historical Perspective: PALs – same technology as programmed once bipolar PROM EPLDs — CMOS erasable programmable ROM (EPROM) erased by UV light Altera building block = MACROCELL 8 Product Term AND-OR Array + Programmable MUX's Programmable polarity I/O Pin Seq. Logic Block Programmable feedback

ECE C03 Lecture 524 Altera EPLDs Altera EPLDs contain 8 to 48 independently programmed macrocells Personalized by EPROM bits: Flipflop controlled by global clock signal local signal computes output enable Flipflop controlled by locally generated clock signal + Seq Logic: could be D, T positive or negative edge triggered + product term to implement clear function Synchronous Mode Asynchronous Mode Global CLK OE/Local CLK EPROM Cell 1 Global CLK OE/Local CLK EPROM Cell 1 Clk MUX Clk MUX Q Q

ECE C03 Lecture 525 LAB ALAB H LAB BLAB G LAB C LAB F LAB D LAB E P I A Altera EPLDs AND-OR structures are relatively limited Cannot share signals/product terms among macrocells Altera solution: Multiple Array Matrix (MAX) Logic Array Blocks (similar to macrocells) Global Routing: Programmable Interconnect Array 8 Fixed Inputs 52 I/O Pins 8 LABs 16 Macrocells/LAB 32 Expanders/LAB EPM5128:

ECE C03 Lecture 526 Altera EPLDs LAB Architecture Expander Terms shared among all macrocells within the LAB Macrocell ARRAY I/O Block Expander Product Term ARRAY I N P U T S P I A I/O Pad Macrocell P-Terms Expander P-Terms

ECE C03 Lecture 527 Altera EPLDs P22V10 PAL 0 ASYNCHRONOUS RESET (TO ALL REGISTERS) 23 AR OUTPUT LOGIC MACROCELL P R OUTPUT LOGIC MACROCELL P R OUTPUT LOGIC MACROCELL P R OUTPUT LOGIC MACROCELL P R DQ Q SP P R INCREMENT FIRST FUSE NUMBERS 15 9 OUTPUT LOGIC MACROCEL L P R OUTPUT LOGIC MACROCEL L P R OUTPUT LOGIC MACROCEL L P R OUTPUT LOGIC MACROCEL L P R OUTPUT LOGIC MACROCEL L P R SYNCHRONOUS PRESET (TO ALL REGISTERS) INCREMEN T Supports large number of product terms per output Latches and muxes associated with output pins

ECE C03 Lecture 528 Actel Programmable Gate Arrays Rows of programmable logic building blocks + rows of interconnect Anti-fuse Technology: Program Once 8 input, single output combinational logic blocks FFs constructed from discrete cross coupled gates Use Anti-fuses to build up long wiring runs from short segments I/O Buffers, Programming and Test Logic Logic ModuleWiring Tracks I/O Buffers, Programming and Test Logic

ECE C03 Lecture 529 Actel Logic Module Basic Module is a Modified 4:1 Multiplexer Example: Implementation of S-R Latch 2:1 MUX D0 D1 SOA 2:1 MUX D2 D3 SOB 2:1 MUX S0 Y S1 2:1 MUX "0" R 2:1 MUX "1" S 2:1 MUX Q "0"

ECE C03 Lecture 530 Actel Interconnect Interconnection Fabric Logic Module Horizontal Track Vertical Track Anti-fuse

ECE C03 Lecture 531 Actel Routing Example Jogs cross an anti-fuse minimize the # of jobs for speed critical circuits hops for most interconnections Logic Module Output Input

ECE C03 Lecture 532 Xilinx Logic Cell Arrays CMOS Static RAM Technology: programmable on the fly! All personality elements connected into serial shift register Shift in string of 1's and 0's on power up General Chip Architecture: Logic Blocks (CLBs) IO Blocks (IOBs) Wiring Channels IOB CLB IOB Wiring Channels

ECE C03 Lecture 533 Xilinx LCA Architecture Inputs: Tri-state enable bit to output input, output clocks Outputs: input bit Internal FFs for input & output paths Fast/Slow outputs 5 ns vs. 30 ns rise Pull-up used with unused IOBs DQ OUT INV TS INV OUTPUT SOURCE SLEW RATE PASSIVE PULLUP MUX R DQ R Vcc PAD Output Buffer TTL or CMOS Input Buffer Global ResetClocks Enable Output Out Direct In Registered In Program Controlled Options

ECE C03 Lecture 534 Xilinx LCA Architecture Configurable Logic Block: CLB 2 FFs Any function of 5 Variables Global Reset Clock, Clock Enb Independent DIN Combinational Function Generator D RD Q CE Mux D RD Q CE Mux A B C D E Q1 Q2 Reset DIN Clock Enable F G X Y

ECE C03 Lecture 535 Xilinx CLB Function Generator CLB Function Generator Any function of 5 variables Two Independent Functions of 4 variables each Function of 5 Variables F G Mux A B C D E Q1 Q2 Function of 4 Variables F Mux A B C D E Q1 Q2 Mux Function of 4 Variables G Mux A B C D E Q1 Q2 Mux

ECE C03 Lecture 536 Xilinx CLB Function Generator Certain Limited Functions of 6 Variables Function of 4 Variables E Mux A B C D Q1 Q2 Function of 4 Variables Mux A B C D Q1 Q2 Mux F G

ECE C03 Lecture 537 Xilinx Application Examples 5-Input Parity Generator Implemented with 1 CLB: F = A xor B xor C xor D xor E 2-bit Comparator: A B = C D or A B > C D Implemented with 1 CLB: (GT) F = A C + A B D + B C D (EQ) G = A B C D + A B C D + A B C D + A B C D (this is a different parity generator than the one in Chapter 8!)

ECE C03 Lecture 538 Xilinx Application Examples n-Input Majority Circuit Assert 1 whenever n/2 or greater inputs are 1 n-input Parity Functions 5 input = 1 CLB, 2 Levels of CLBs yield up to 25 inputs! CLB 5-input Majority Circuit CLB 7-input Majority Circuit CLB 9 Input Parity Logic

ECE C03 Lecture 539 Xilinx Application Examples 4-bit Binary Adder CLB A0B0Cin S0 CLB A1B1 S1 CLB A2B2 C1 S2 CLB A3B3 C2 S3C0 Cout S0 S1 C2 A1B1CinA0B0 CLB S2 S3 Cout A3B3A2B2 CLB Full Adder, 4 CLB delays to final carry out 2 x Two-bit Adders (3 CLBs each) yields 2 CLBs to final carry out

ECE C03 Lecture 540 Xilinx Interconnect Architecture Interconnect Direct Connections Global Long Line Horizontal/Vertical Long Lines Switching Matrix Connections X Y CLB3 A D DI B C K ER CE X Y CLB1 A D DI B C K ER CE X Y CLB0 A D DI B C K ER CE Direct Connections Horizontal Long Line Vertical Long Lines Global Long Line Switching Matrix Horizontal Long Line X Y CLB2 A D DI B C K ER CE

ECE C03 Lecture 541 Comparison of Recent Xilinx Architectures

ECE C03 Lecture 542 Summary Combinational Logic Implementations Multiplexers Decoders ROMS Field Programmable Logic Arrays READING: Katz 4.2.2, 4.2.3, 4.2.4, 4.2.5, 10.3, Dewey 5.7