ZPD Overview Stephen Bailey Harvard University ZPD Conceptual Design Review 11 September 2001

11 Sept 01S. Bailey, ZPD Overview2 ZPD: z p T Discriminator Purpose Select tracks from interactions at z 0  0 and reject background tracks from |z 0 |>20 cm Measure p T of tracks for triggering Constraints Latency < 2.2  s Process more than GB/sec of input data per ZPD

11 Sept 01S. Bailey, ZPD Overview3 Input Data Up to 3 segs per superlayer (SL) per 1/16 in azimuth (  ) Each seg has SL,  position, and error d  Stereo SL (U and V) segs have offset in  Each ZPD gets segs from 3/8 in  Reports tracks from seed segs in central 1/8 of coverage (8 ZPDs total) A1 U2 V3 A4 U5 V6 A7 U8 V9 A10                                         

11 Sept 01S. Bailey, ZPD Overview4 Clocks ClockFrequencyPeriodComment CLK4CLK4 / ns Compete set of data arrives from TSFs CLK8CLK4 / 8134 nsOutput to GLT CLK MHz16.8 nsBasic ZPD clock CLK120CLK4 x 28.4 ns Data transport and/or algorithm FPGAs CLK180CLK4 x 35.6 ns Data transport and/or algorithm FPGAs

11 Sept 01S. Bailey, ZPD Overview5 ZPD Output Can make decision on combination of z 0 p T tan 6 bits of decision output Initially only 4 will be used 2 different decisions, covering 1/16 each 4 different decisions, covering 1/8 each 2 decisions covering 1/8 and 1+1 covering 1/16 2 extras for future upgrades

11 Sept 01S. Bailey, ZPD Overview6 ZPD Block Diagram

11 Sept 01S. Bailey, ZPD Overview7 ZPD Interface Board (ZPDi) Receives data from 9 TSFs 6 TSFx with 21 segments each 3 TSFy with 18 segments each Pass 153/180 segments through backplane Not all are needed for p T coverage Initial design uses 144 segments Send trigger decision to GLT

11 Sept 01S. Bailey, ZPD Overview8 Data Receiver and Fast Control Data Receiver Receives and reformats segment data Drives MegaBus to Algorithm FPGAs Fast Control Receives triggers, clocks, and commands Returns diagnostic and DAQ data

11 Sept 01S. Bailey, ZPD Overview9 MegaBus Need to transport ~160 bits of data at 60 MHz LVDS bus 80 bits at 120 MHz (or 54 bits at 180 MHz) Pros: Low noise, low power Cons: on board termination required Single Ended 160 bits at 60 MHz Pros: Xilinx provides termination internal to FPGAs Cons: speed, noise Building prototype to test options Upcoming details: John Oliver

11 Sept 01S. Bailey, ZPD Overview10 Algorithm Engines Find tracks and fit for z 0, 1/p T, and tan Process 2 or 3 seed segments serially 2 seeds at 120 MHz: 6 FPGAs needed 3 seeds at 180 MHz: 4 FPGAs needed

11 Sept 01S. Bailey, ZPD Overview11 Seed Track Finder Purpose Find seed tracks Find segments on those tracks Input Segment data (SL, , and d  ) Output for each seed segment Seed track p T and tan Segments on seed track

11 Sept 01S. Bailey, ZPD Overview12 Seed Track Finder Algorithm Upcoming details: Nick Sinev

11 Sept 01S. Bailey, ZPD Overview13 Track Fitter Purpose: fit track for 1/p T, tan, and z 0 Input 1/p T and tan of a seed track Segments on that track Output Improved 1/p T and tan z 0 measurement and error Superlayer segment map

11 Sept 01S. Bailey, ZPD Overview14 Track Fitter Algorithm Fit in r-  to improve 1/p T measurement Using diff in  between track and stereo seg’s, find z of each stereo segment Fit stereo seg’s in r-z to obtain z 0 and tan Upcoming details: Masahiro Morii

11 Sept 01S. Bailey, ZPD Overview15 Decision Module Input from each seed track z 0, error on z 0, 1/p T, tan, hit map 4 to 6 bits of trigger output “Is there a track with |z 0 | < [x] cm?” “Is there a track with p T > [y] MeV/c?” More sophisticated combinations Upcoming performance details: Valerie Halyo

11 Sept 01S. Bailey, ZPD Overview16 Diagnostic I/O Memories Aid debugging through recording and playback of datastream 17.2  s deep (64 CLK4s) Every CLK4: Input: 144 segments x 16 bits each Intermediate: Track Finder and Fitter results 1/p T, tan, segments on tracks, z 0, … 189 bits/engine x 12 engines Output: 6 decision bits

11 Sept 01S. Bailey, ZPD Overview17 DAQ Memories DAQ memories store information to be read out with each triggered event Much smaller than diagnostic I/O memories due to DAQ bandwidth limitations Input: which segments were received 144 bits/CLK4 Output: Z Fitter results plus decisions 38x12+6=462 bits/CLK4 Both diagnostic and DAQ memories will be implemented internal to the FPGAs

11 Sept 01S. Bailey, ZPD Overview18 Latency Considerations Latency must be < 2.2  s New data arrives every 269 ns (CLK4 period)

11 Sept 01S. Bailey, ZPD Overview19 Summary of Challenges MegaBus Prototype to test several technology choices Finder/Fitter FPGAs Size drives the cost of the board Aggressive schedule Need working ZPDs in ~1 year Do a full board simulation before production Performance Initial results are promising

11 Sept 01S. Bailey, ZPD Overview20 Upcoming Talks Finder details: Nick Sinev Fitter details: Masahiro Morii Physics performance: Valerie Halyo Engineering issues: John Oliver Schedule: John Oliver Cost and resources: Masahiro Morii