1. Trigger for MEG2: status and plans Donato Nicolo` Pisa (on behalf of the Trigger Group) Lepton Flavor Physics with Most Intense DC Muon Beam Fukuoka, 22 October 2013

2. Outlook Current scheme Short-term objectives (by end 2013) –Hardware (FPGA) selection –Data bus transmission-reception –Latency vs serialization factor –Backplane bus definition –Start concentrator board design Long-term agenda (2014) –Board design and construction –Trigger bus protocol and algorithm implementation –Tests Trigger for MEG2:...2

3. Critical issues and new features Data bus handshaking –WaveDREAM  trigger concentrator Expected throughput : 60 bit x 80 Mhz ~ 5 Gb/s from each WD  Up to ~80Gb/s data load on a low-level trigger concentrator (twice larger than current Master Type2 board) with data serialization  SERDES –trigger  trigger Connections from/to different crates  synchronous CLK needed, with the possibility to use different skews 2nd level trigger –algorithms LUTs for hit lists  track segments mapping to be implemented onto associative memory chips –options Search on single board (track info to be transmitted to upper level board) Track finder operated on master concentrator CLK synchorization Backplane design and routing, master-slave protocol definition Trigger for MEG2:...3

4. Serialization and latencies Spartan 6 SERDES Trigger for MEG2:...4 WD side IOB guaranteed up to 1050 Mb/s  6 OSERDES on each WaveDREAM with 10:1 serialization on Spartan6 Implemented with MMCM/PLL for CLK multiplication DATA stream in DDR mode (i.e. on both edges of the forwarded CLK) trigger concentrator side ~100 ISERDES needed to collect data from 16 WDs  need to use series 7 FPGAs (where all IOB can be used as differential ISERDES ports) Need to use also a different IDE (VIVADO instead of ISE) Virtex 7 Kintex 7 Artix 7 Low cost and power consumption Resources and performances

5. Trigger, data transmission test Xilinx evalutation boards been purchased and delivered by the end of August –AES-S6PCIE-LX75T-G (utilizes Spartan 6 XC6SLX75T-3FGG676C) cost 352 E –EK-K7-KC705-G (Kintex 7, XC7K325T-2FFG900C) 1440 E Trigger for MEG2:...5

6. The test bench Trigger for MEG2:...6 RTL schematic on Kintex 7, Vivado output on 15/10/2013 OSERDES ISERDES Dual-Port RAMs PLL for transmission CLK  -processor

7. First checks Trigger for MEG2:...7 check master and internal clocks through connection to FMC connectors DATA & CLK output connected to input check whether memory content is the same and how input memory shifted it is wrt output

8. PLL check on output connector Trigger for MEG2:...8

9. Results on data serialization Trigger for MEG2:...9 Data given by the output of a 5 bit counter Transmission OK 4 CLK ticks latency confirmed  OK (used to be 8) to be checked with random patterns (failure rate as a function of delay)

10. Backplane connectivity Star connectivity for SERDES Slave Select Bus connectivity for SPI (except SS) MISC Clock Trigger Bus Serial Peripheral Interface Bus Trigger for MEG2:...10 From Stefan’s presentation in Osaka

11. Backplane 18 diff pairs – 12.5 Gb/s Elettronica per MEGup11 Preliminary assignment 5 times Up to 8 pairs available for each WD  concentrator connection Obtain the best trade off between latency and connectivity

12. Backplane route constraints Elettronica per MEGup12 Power lines Master/Slave SPI One reference CLK –must be synchronously distributed (net length spread<O(10ps))  to be routed on a dedicated plane in the circuit stack-up? Trigger bus –TRIGGER  skew < 100 ps –SYNC –BUSY –EV.NUMBER+ID CODE (serial) Data lines  skew < 500 ps (adjustable IOB delays)

13. TCB  TCB link Elettronica per MEGup13 Low level (~40 boards) –60 output bits from any TCB, again 10:1 serialization  6 data+1 CLK output  2 HDMI front D-type connectors Intermediate level (~10 boards) –Fan-in 4:1  8 HDMI D-type input connectors –Data output to master TCB through the backplane connector (the same as in the case of WD)  direction inverted wrt low level boards –compatibility can be guaranteed Top level (1 master board) –Located in the same crate as intermediate boards –Receives data and CLK from the backplane (the same way of low level boards)

14. Schedule for 2014 Trigger for MEG2:...14 01/201412/2014

15. Conclusions Evaluation kits for Xilinx FPGA been purchased Serial data transmission/reception successfully implemented with SERDES protocol on Kintex7 FPGA –Latency in agreement with expectations  not a concern –Massive test needed for bit-deskew optimization To be repeated on Spartan6  Kintex7 connection before final choice Preliminary backplane bus assignment done –final constraints to be decided before starting concentrator board design  before the end of the year Trigger for MEG2:...15