1. 10-09-2004 Wilco Vink 1 Outline Optical station Vertex processor board Output board Latency

2. 10-09-2004 Wilco Vink 2 VETO Dataflow

3. 10-09-2004 Wilco Vink 3 VETO Optical Station Single 9U crate (with 3u power backplane) 8 Optical transmitter boards cat5 cables fed in from rear via transition boards(32 RJ45 inputs each) 1 control unit tbd (ttc) –Possibly replaced by VELO ECS

4. 10-09-2004 Wilco Vink 4 Veto optical transmitter Board Inputs: 128 lvds pairs @80Mb/s Synchronize inputs (de- skew/ differences in cable length) Data demultiplexing Queuing event fragments 12 GOL serializers Output: 1 optical ribbon

5. 10-09-2004 Wilco Vink 5 Synchronize differences in cable length Input data @80Mb/s from beetle chips Synchronization clock, selectable via i2c Maximum allowed channel to channel skew: 1 period(12.5 ns)

6. 10-09-2004 Wilco Vink 6 Status Optical Transmitter Board Completed: –Functional design FPGA’s –Full timing simulation In progress: –Schematic entry To be done: –Layout (dec. 2004)

7. 10-09-2004 Wilco Vink 7 VETO Dataflow

8. 10-09-2004 Wilco Vink 8 Veto vertex Processor Board Vertex finder in Xilinx Virtex2Pro – type XC2VP100ff1704-5 2 O-rx Optical input Cards Credit Card PC and Glue Card TTCrq Mezzanine Card Trigger decision on 1 copper serial link to output board 2 optical outputs to L1 buffer/DAQ (TELL1)

9. 10-09-2004 Wilco Vink 9 Functional diagram

10. 10-09-2004 Wilco Vink 10 VEPROB (Vertex PROcessor Board) Done: -VHDL programming algorithm -simulation VHDL -schematic entry Ongoing: -Layout

11. 10-09-2004 Wilco Vink 11 Output board 4 serial inputs from vertex processor boards Sole functionality: multiplex trigger data towards L0DU Xilinx FPGA with Rocket I/O 2 fibers optical output CCPC to configure, debug, monitor TTCrq

12. 10-09-2004 Wilco Vink 12 VETO Latency LHC Clocks Hybrid 50ns 2 Cabling to optical station 6ns/m108 ns 5 VETO Optical StationSynchronisation and demultiplexing 4 GOL 64 ns max 3 Optical Ribbon60m (4.5ns/m) 270 ns 11 Vertex processor board Orx-card(tlk2501) 4 channel sync and vertex finder algoritm(xilinx FPGA) 1050ns 42 MGT Rocket i/o transmitter + cable 4 Output boardMGT Rocket i/o receiver 4 Mux 1 MGT Rocket i/o transmitter 3 Cable to L0DU 90ns 4 Total: 87