Implementing Digital Circuits Lecture L3.1

Implementing Digital Circuits Transistors and Integrated Circuits Transistor-Transistor Logic (TTL) Programmable Logic Devices –PLDs and CPLDs Field Programmable Gate Arrays (FPGAs) –The Xilinx Spartan 3 –The Xilinx Virtex Family

Discovery of the Electron J. J. Thomson Cathode Tube Cavendish Labs Electric Field -- “corpuscle”

The Vacuum Tube

The First Point-Contact Transistor 1947 Bell Labs Museum

The First Junction Transistor 1951 Bell Labs Lab model M1752 Outside the Lab

Texas Instrument’s First IC Jack Kilby Robert Noyce Fairchild Intel

Moore’s Law

Implementing Digital Circuits Transistors and Integrated Circuits Transistor-Transistor Logic (TTL) Programmable Logic Devices –PLDs and CPLDs Field Programmable Gate Arrays (FPGAs) –The Xilinx Spartan 3 –The Xilinx Virtex Family

Transistor-Transistor Logic (TTL) Developed in mid-1960s Large family (74xx) of chips from basic gates to arithmetic logic units Becoming obsolete with the development of programmable logic devices (PLDs)

Transistor-Transistor Logic (TTL) Diode-Transistor Logic DTL Transistor-Transistor Logic (TTL) "Totem Pole" output

TTL Chips

TTL NAND, NOR, XOR

TTL Multiple-input Gates

Small-Scale Integrated (SSI) Circuits 1 to 10 gates NAND gate has 4 transistors

Medium-Scale Integrated (MSI) Circuits gates Adders Comparators Multiplexers Decoders

Large-Scale Integrated (LSI) Circuits gates Arithmetic Logic Units

Very-Large-Scale Integrated (VLSI) Circuits >1000 gates Microprocessors Programmable Logic Devices (PLDs) Complex Programmable Logic Devices (CPLDs) Field Programmable Gate Arrays (FPGAs)

Implementing Digital Circuits Transistors and Integrated Circuits Transistor-Transistor Logic (TTL) Programmable Logic Devices –PLDs and CPLDs Field Programmable Gate Arrays (FPGAs) –The Xilinx Spartan 3 –The Xilinx Virtex Family

A Programmable Logic Device

A = X & !X & Y & !Y = 0 & 0 = 0

A Programmable Logic Device A = X & !X & Y & !Y = 0 & 0 = 0 Z = A # B = 0 # B = B

Alternate PLD Representation

Make PLD Connections for AND XY X!XY!Y A B Z 1 2 XX XXXX

Make PLD Connections for OR XY X!XY!Y A B Z 1 2 X X

Make PLD Connections for NAND XY X!XY!Y A B Z 1 2 X X

Make PLD Connections for NOR XY X!XY!Y A B Z 1 2 XX XXXX

Make PLD Connections for XNOR XY X!XY!Y A B Z 1 2 XX XX A B C

Make PLD Connections for XOR XY X!XY!Y A B Z 1 2 XX XX A B C

The GAL 16V GND Vcc I/CLK II/O I I I I I I I I/OE I/O GAL 16V8

Structure of the GAL 16V8 PLD

GAL 16V8 Polarity Control OE X A B C X closed B = 0 C = A ­ open B = 1 C = !A Polarity Pin

Typical PLD Flip-Flops

Structure of the GAL 16V8 PLD

XC9500 CPLDs 5 volt in-system programmable (ISP) CPLDs 5 ns pin-to-pin 36 to 288 macrocells (6400 gates) Industry’s best pin- locking architecture 10,000 program/erase cycles Complete IEEE JTAG capability Function Block 1 JTAG Controller Function Block 2 I/O Function Block 4 3 Global Tri-States 2 or 4 Function Block 3 I/O In-System Programming Controller FastCONNECT Switch Matrix JTAG Port 3 I/O Global Set/Reset Global Clocks I/O Blocks 1

XC9500 Function Block To FastCONNECT From FastCONNECT 2 or 4 3 Global Tri-State Global Clocks I/O 36 Product- Term Allocator Macrocell 1 AND Array Macrocell 18 Each function block is like a 36V18 !

XC9500 Product Family 9536 Macrocells Usable Gates t PD (ns) Registers Max I/O Packages VQ44 PC44 PC84 TQ100 PQ100 PC84 TQ100 PQ100 PQ160 PQ100 PQ HQ208 BG352 PQ160 HQ208 BG

PLDT-3 Xilinx XC95108 CPLD 7 segment display Switches LEDs Buttons

Xilinx function blocks –Each contains 18 macro cells –Each macro cell behaves like a GAL32V18 AND-OR array for sum-of-products 32 inputs and 18 outputs

Architecture of the Xilinx XC95108 CPLD

Each Xilinx macrocell contains a D flip-flop Controlled inverter

Each Xilinx macrocell contains a D flip-flop Note asynchronous preset x Note asynchronous reset y z

Implementing Digital Circuits Transistors and Integrated Circuits Transistor-Transistor Logic (TTL) Programmable Logic Devices –PLDs and CPLDs Field Programmable Gate Arrays (FPGAs) –The Xilinx Spartan 3 –The Xilinx Virtex Family

Block diagram of Xilinx Spartan-3 FPGA

Each Spartan-3 CLB contains four CLB slices

Left-hand Slice SLICEM

Top of Left-hand Slice SLICEM

16 x 1 SRAM Lookup Table

Look Up Tables  Capacity is limited by number of inputs, not complexity  Choose to use each function generator as 4 input logic (LUT) or as high speed sync.dual port RAM Combinatorial Logic is stored in 16x1 SRAM Look Up Tables (LUTs) in a CLB Example: A B C D Z Look Up Table Combinatorial Logic A B C D Z 4-bit address G Func. Gen. G4 G3 G2 G1 WE 2 (2 ) 4 = 64K !

Center of Left-hand Slice SLICEM

Bottom of Left-hand Slice SLICEM

Xilinx Spartan-3 FPGAs

Block RAM

Digital Clock Manager (DCM)

Delay-Locked Loop (DLL)

Implementing Digital Circuits Transistors and Integrated Circuits Transistor-Transistor Logic (TTL) Programmable Logic Devices –PLDs and CPLDs Field Programmable Gate Arrays (FPGAs) –The Xilinx Spartan 3 –The Xilinx Virtex Family

Virtex FPGAs For info on Virtex 1000 boards, see

Virtex-II FPGAs

Virtex-II Pro FPGAs

CPLDs vs. FPGAs

Virtex-4 FPGAs