ECE C03 Lecture 91 Lecture 9 Registers, Counters and Shifters Hai Zhou ECE 303 Advanced Digital Design Spring 2002

ECE C03 Lecture 92 Outline Registers Register Files Counters Designs of Counters with various FFs Shifters READING: Katz 7.1, 7.2, 7.4, 7.5, 4.7 Dewey 10.2, 10.3, 10.4, Hennessy-Patterson B26

ECE C03 Lecture 93 Building Complex Memory Elements Flipflops: most primitive "packaged" sequential circuits More complex sequential building blocks: Storage registers, Shift registers, Counters Available as components in the TTL Catalog How to represent and design simple sequential circuits: counters Problems and pitfalls when working with counters: Start-up States Asynchronous vs. Synchronous logic

ECE C03 Lecture 94 Registers Storage unit. Can hold an n-bit value Composed of a group of n flip-flops –Each flip-flop stores 1 bit of information Normally use D flip-flops D Q Dff clk D Q Dff clk D Q Dff clk D Q Dff clk

ECE C03 Lecture 95 Controlled Register D Q Dff clk D Q Dff clk D Q Dff clk D Q Dff clk

ECE C03 Lecture 96 Registers Group of storage elements read/written as a unit 4-bit register constructed from 4 D FFs Shared clock and clear lines TTL Quad D-type FF with Clear (Small numbers represent pin #s on package) Schematic Shape

ECE C03 Lecture 97 Shift Registers Storage + ability to circulate data among storage elements Shift from left storage element to right neighbor on every lo-to-hi transition on shift signal Wrap around from rightmost element to leftmost element Master Slave FFs: sample inputs while clock is high; change outputs on falling edge Shift Direction \Reset Shift JKJK JKJK JKJK JKJK QQQQ QQQQ QQQQ QQQQ Q1 Q2 Q3 Q4

ECE C03 Lecture 98 Shift Registers I/O Serial vs. Parallel Inputs Serial vs. Parallel Outputs Shift Direction: Left vs. Right bit Universal Shift Register Serial Inputs: LSI, RSI Parallel Inputs: D, C, B, A Parallel Outputs: QD, QC, QB, QA Clear Signal Positive Edge Triggered Devices S1,S0 determine the shift function S1 = 1, S0 = 1: Load on rising clk edge synchronous load S1 = 1, S0 = 0: shift left on rising clk edge LSI replaces element D S1 = 0, S0 = 1: shift right on rising clk edge RSI replaces element A S1 = 0, S0 = 0: hold state Multiplexing logic on input to each FF! Shifters well suited for serial-to-parallel conversions, such as terminal to computer communications QD QC QB QA

ECE C03 Lecture 99 Application of Shift Registers Parallel to Serial Conversion QA QB QC QD S1 S0 LSI D C B A RSI CLK CLR QA QB QC QD S1 S0 LSI D C B A RSI CLK CLR D7 D6 D5 D4 Sender D3 D2 D1 D0 QA QB QC QD S1 S0 LSI D C B A RSI CLK CLR QA QB QC QD S1 S0 LSI D C B A RSI CLK CLR Receiver D7 D6 D5 D4 D3 D2 D1 D0 Clock 194 Parallel Inputs Serial transmission Parallel Outputs

ECE C03 Lecture 910 Counters Proceed through a well-defined sequence of states in response to count signal 3 Bit Up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000,... 3 Bit Down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111,... Binary vs. BCD vs. Gray Code Counters A counter is a "degenerate" finite state machine/sequential circuit where the state is the only output A counter is a "degenerate" finite state machine/sequential circuit where the state is the only output

ECE C03 Lecture 911 Counter Design Procedure This procedure can be generalized to implement ANY finite state machine Counters are a very simple way to start: no decisions on what state to advance to next current state is the output Example:3-bit Binary Upcounter State Transition Table Flipflop Input Table Decide to implement with Toggle Flipflops What inputs must be presented to the T FFs to get them to change to the desired state bit? This is called "Remapping the Next State Function" Present State Next State Flipflop Inputs C B A C+ B+ A+ TC TB TA

ECE C03 Lecture 912 Example Design of Counter K-maps for Toggle Inputs: Resulting Logic Circuit: CB A 0 1 TA = CB A 0 1 TB = CB A 0 1 TC =

ECE C03 Lecture 913 Resultant Circuit for Counter K-maps for Toggle Inputs: Resulting Logic Circuit: Timing Diagram: T CLK \Reset Q Q S R QA T CLK Q Q S R QB T CLK Q Q S R QC Count +

ECE C03 Lecture 914 More Complex Counter Design Step 1: Derive the State Transition Diagram Count sequence: 000, 010, 011, 101, 110 Step 2: State Transition Table Present State Next State

ECE C03 Lecture 915 Complex Counter Design (Contd) Step 1: Derive the State Transition Diagram Count sequence: 000, 010, 011, 101, 110 Step 2: State Transition Table Note the Don't Care conditions Present State Next State X X X X X X X X X

ECE C03 Lecture 916 Counter Design (Contd) Step 3: K-Maps for Next State Functions CB A 0 1 C+ = CB A 0 1 A+ = CB A 0 1 B+ =

ECE C03 Lecture 917 Counter Design (contd) Step 4: Choose Flipflop Type for Implementation Use Excitation Table to Remap Next State Functions Toggle Excitation Table Remapped Next State Functions Present State Toggle Inputs Q Q+ T X X X X X X X X X C B A TC TB TA

ECE C03 Lecture 918 Resultant Counter Design Remapped K-Maps CB A 0 1 TC CB A 0 1 TA CB A 0 1 TB TC = A C + A C = A xor C TB = A + B + C TA = A B C + B C

ECE C03 Lecture 919 Resultant Circuit for Complex Counter Resulting Logic: Timing Waveform: 5 Gates 13 Input Literals + Flipflop connections TC T CLK Q Q S R Count T CLK Q Q S R TB C \C BA \B \A TA T CLK Q Q S R \Reset TC TB TA ACAC A \B C \A B C \B C

ECE C03 Lecture 920 Implementing Counters with Different FFs Different counters can be implemented best with different FFs Steps in building a counter –Build state diagram –Build state transition table –Build next state K-map Implementing the next state function with different FFs Toggle flip flops best for binary counters Existing CAD software for finite state machines favor D FFs

ECE C03 Lecture 921 Implementing 5-state counter with RS FFs Continuing with the 000, 010, 011, 101, 110, 000,... counter example RS Exitation Table Remapped Next State Functions Q+ = S + R Q Present State Next State X X X X X X X X X X X X 0 0 X X X X X X X X X X X X X X X X X X X X X X Q Q+ R S 0 0 X X Rmepped next state RC SC RB SB RA SA

ECE C03 Lecture 922 Implementation with RS FFs RS FFs Continued RC = A SC = A RB = A B + B C SB = B RA = C SA = B C CB A 0 1 RC CB A 0 1 RA CB A 0 1 RB CB A 0 1 SC CB A 0 1 SA CB A 0 1 SB X X 1 X X X X 1 X X X X 1 X 0 1 X 0 X X 0 X 1 X 0 X X X 0 X X X X X 0

ECE C03 Lecture 923 Implementation With RS FFs Resulting Logic Level Implementation: 3 Gates, 11 Input Literals + Flipflop connections CLK \A R SA C \C Q Q RB \B R S Q Q \B B C SA R S A \A B A C B \C RBSA Q Q Count

ECE C03 Lecture 924 Implementing with JK FFs Continuing with the 000, 010, 011, 101, 110, 000,... counter example RS Exitation Table Remapped Next State Functions Q+ = S + R Q Present State Next State Q Q+ J K X X 1 0 X X 0 Rmepped next state JC KC JB KB JA KA X 1 X 0 X X X X X X X X X X X X 0 1 X X X 1 X X X X X X X X X X X 0 1 X X X 1 X 1 0 X X X X X X X X X X

ECE C03 Lecture 925 Implementation with JK FFs CB A 0 1 JC CB A 0 1 JA CB A 0 1 JB CB A 0 1 KC CB A 0 1 KA CB A 0 1 KB JC = A KC = A/ JB = 1 KB = A + C JA = B C/ KA = C

ECE C03 Lecture 926 Implementation with JK FFs Resulting Logic Level Implementation: 2 Gates, 10 Input Literals + Flipflop Connections CLK J K Q Q A \A C \C KB J K Q Q B \B + J K Q Q JA C A \A B \C Count A C KB JA

ECE C03 Lecture 927 Implementation with D FFs Simplest Design Procedure: No remapping needed! DC = A DB = A C + B DA = B C Resulting Logic Level Implementation: 3 Gates, 8 Input Literals + Flipflop connections

ECE C03 Lecture 928 Comparison with Different FF Types T FFs well suited for straightforward binary counters But yielded worst gate and literal count for this example! No reason to choose R-S over J-K FFs: it is a proper subset of J-K R-S FFs don't really exist anyway J-K FFs yielded lowest gate count Tend to yield best choice for packaged logic where gate count is key D FFs yield simplest design procedure Best literal count D storage devices very transistor efficient in VLSI Best choice where area/literal count is the key

ECE C03 Lecture 929 Summary Registers Register Files Counters Designs of Counters with various FFs NEXT LECTURE: Memory Design READING: Katz 7.6