Cost-Based Tradeoff Analysis of Standard Cell Designs Peng Li Pranab K. Nag Wojciech Maly Electrical and Computer Engineering Carnegie Mellon University Pittsburgh, PA {pli, pkn,

2P. Li, SLIP’2000 Motivations  Necessity for Evaluation of Designs’ Cost Effectiveness –Tendency of Manufacturing Cost Increase –Selection of Technology Which Yields the Least Cost  Emergence of Fabless Design Houses –Choice of Manufacturing Technologies –Consideration of Manufacturing from Design Perspective  Importance of Early-Stage Predictions –Reduction of Number of Design Iterations –Facilitation of Early-Stage Decision

3P. Li, SLIP’2000 Objective  Cost Prediction for Standard Cell Designs –Quickly Predict Die Size & Interconnect Yield As a Function of Number of Metal Layers  Based On a Given Placement –Predict Die Cost Based on a Wafer Cost Model –Forecast Optimal Selection of Number of Metal Layers In Terms Of Die Cost

4P. Li, SLIP’2000 Why Number of Metal Layers Matters  Affect Die Size and Yield  An Important Cost Factor

5P. Li, SLIP’2000 Approach Given Placement Stochastic Pseudo-Routing (Routing Estimation) Stochastic Pseudo-Routing (Routing Estimation) Die Height Estimation Die Width Estimation Size Estimate Stable? Size Estimate Stable? Interconnect Critical Area Analysis Interconnect Critical Area Analysis Interconnect Yield Prediction Interconnect Yield Prediction Cost Prediction

6P. Li, SLIP’2000 Stochastic Pseudo Routing Stochastic Pseudo-Routing Defects Expanded/Compacted Placement Given Placement Estimated Routing Utilization Interconnect Yield Prediction Wafer Cost Model

7P. Li, SLIP’2000 Layout Representation  Grid Routing Model –Horizontal Routing Layers: Metal1, Metal3, Metal5 etc. –Vertical Routing Layers: Metal2, Metal4, Metal6 etc. Cell height defined by cell library Channel Grids Cell-Row Grids Channel height to be estimated Chip width to be estimated Grid width

8P. Li, SLIP’2000 Stochastic Pseudo Routing of Two-terminal Nets  Restrict routing estimation within the bounding box of the net.  Only consider Manhattan paths having no more than two vias.  There are totally PNUM = (M+N-2) path candidates.  Assume each path candidate has a probability of 1/PNUM of being selected. N M

9P. Li, SLIP’2000 Stochastic Pseudo Routing of Two-terminal Nets  From Probabilities To Routing Utilization Estimates p1 p2 p1 p2 p3 p4 p1 p2 p1 p2 p4 p3

10P. Li, SLIP’2000  Extension of Pseudo Routing of Two-Terminal Nets –Find A Minimum Spanning Tree –Pseudo Route Each Edge of The MST –Consider wiring sharing among MST Edges  Assume Pseudo-Routing of MST edges are independent of each other: Stochastic Pseudo Routing of Multi-Terminal Nets Pin1 Pin5 P4 Pin2 Pin3 Merged Segment Merged Region p1 p2 p4 p5 p3

11P. Li, SLIP’2000 Die Size Estimation Stochastic Pseudo-Routing Defects Expanded/Compacted Placement Given Placement Estimated Routing Utilization Interconnect Yield Prediction Wafer Cost Model

12P. Li, SLIP’2000 Die Height Estimation  Lower Bound of Total Channel Density –Based on horizontal routing utilization estimation. –“Switchable Routing Demand”  Analogy to switchable net segments –Assign “switchable routing demand” to proper channels to minimize total channel density. Channel Density: 4 Channels Cell Rows

13P. Li, SLIP’2000 Die Width Estimation  Expand/Compact based on difference between routing demand and capacity.  Iterate on updated cell locations. Compaction Expansion Estimated Vertical Routing Utilization

14P. Li, SLIP’2000 Interconnect Yield Prediction Stochastic Pseudo-Routing Defects Expanded/Compacted Placement Given Placement Estimated Routing Utilization Interconnect Yield Prediction Wafer Cost Model

15P. Li, SLIP’2000 Interconnect Yield Prediction  Traditional Methods –Layout Based Critical Area Extraction  Requires final layouts  Accurate but time consuming: Mapex, Dracula –High-Level Interconnect Model  Relates the yield to netlist characteristics  Our Approach –Based On Routing Utilization Estimation  Empirical Routing Heterogeneity Model  Closed-Form Critical Area Expression –Linear Time Algorithm

16P. Li, SLIP’2000 Cost Prediction Stochastic Pseudo-Routing Defects Expanded/Compacted Placement Given Placement Estimated Routing Utilization Interconnect Yield Prediction Wafer Cost Model

17P. Li, SLIP’2000 Cost Prediction  Wafer Cost Model of 0.25  m CMOS Process  Prediction of Cost As Function of Number of Metal Layers –Number of Good Dies Per Wafer: N good (M) = A wafer / A die (M) ·Yield(M) –Cost of A Good Die: C die (M) = C wafer (M) / N good (M)

18P. Li, SLIP’2000 Experimental Results  Experiment Setup –Six Standard Cell Designs  Portions of Industrial DSP circuits –Comparison With Data Based On Layouts  2-4 metal layers  Our method : die size, routing utilization and yield  Cadence tools: layout generation, critical area extraction(Dracula) and yield calculation

19P. Li, SLIP’2000 Experimental Results  Die Size Estimation Design AreaCadence Estimated % Error 2 Metal 3 Metal 4 Metal

20P. Li, SLIP’2000 Experimental Results Estimated Routing Distribution Distribution Generated by Route Tool Heavily Routed Areas  Routing Utilization Distribution

21P. Li, SLIP’2000 Experimental Results  Yield Prediction Design Cadence Estimated 2 Metal 3 Metal 4 Metal Yield

22P. Li, SLIP’2000 Experimental Results  Optimal Number of Metal Layers Design3Design5  Cost As a Function of Metal Layers Cost($)

23P. Li, SLIP’2000 Summary  Fast Routing Estimation Technique –Die Size –Routing Utilization Distribution –Interconnect Yield Prediction  Cost Prediction –Prediction of Optimal Number of Metal Layers  Directions –A Priori Wire Distribution/Placement Estimation  Standard cell design style  Realistic wiring density distribution –Consideration of Circuit Performance Issues