1. Congestion Estimation and Localization in FPGAs: A Visual Tool for Interconnect Prediction David Yeager Darius Chiu Guy Lemieux The University of British Columbia Department of Electrical and Compute Engineering SLIP 2007

2. Outline Motivations for congestion localization heuristics. Exploring heuristics  Post-placement  Pre-placement Results Future Work SLIP 2007

3. 3 FPGAs: FIXED Routing Architecture SLIP 2007 Fixed Channel Width. Over 80% of resources devoted to interconnect. Comprised of repeated tiles.  Routing resources identical throughout. Can potentially have enough logic resources, not enough routing resources for a design.

4. 4 FPGA Routing Architecture Design SLIP 2007 Architecture design involves retargetable CAD flow.  Cover large amount of customer benchmarks. Routing resources accommodate majority of customer designs that fit in FPGA's logic resources.  Requires excessive amount of fixed interconnect. FPGA Architecture design involves retargetable CAD flow.  Explore different amounts of routing resources.  Select routing that performs best across all circuits. Less fixed routing = higher density, performance. Less fixed routing = more unroutable designs. More fixed routing = more wastage.  Can use 100% of logic resource.  Can never use 100% of routing resources.  Results in excess programmable interconnect. Congestion aware CAD improves routability. Allows architects to get away with less excess programmable interconnect.

5. 5 FPGA vs ASIC Congestion Impact SLIP 2007 Two CAD flows. All results are equal EXCEPT... Only one produces evenly distributed interconnect. ASIC world => No major advantage. FPGA world => Smaller channel width. Allows for denser FPGA architecture. Reduces interconnect wastage. Locating congestion can help with this balancing.

6. 6 Balanced Routing SLIP 2007 waste

7. 7 Balanced Routing: Denser FPGA SLIP 2007 Channel Width = 7 Channel Width = 3

8. 8 Further Motivations for Congestion Localization SLIP 2007 High quality congestion estimation can be slow. May not be realistic to constantly update with every move. Localization can give different weights to different nets, CLBs, LUTs. Update weights during intervals. Example application: SA optimization, Un/Dopack.

9. 9 Motivations for accurate congestion estimation: Un/DoPack SLIP 2007 depopulated clustering incremental place incremental route clusterplaceroute channel width constraint met? success failure start with netlist congestion calculator available area left? yes no channel width constraint met? yes no

10. 10 Motivations: Un/DoPack SLIP 2007 depopulated clustering incremental place route clusterplace route channel width constraint met? success failure start with netlist congestion calculator available area left? yes no channel width constraint met? yes no congestion calculator no

11. 11 Motivations: Un/DoPack SLIP 2007 depopulated clustering place route cluster place route channel width constraint met? success failure start with netlist congestion calculator available area left? yes no channel width constraint met? yes no congestion calculator yes no

12. 12 Motivations for accurate congestion localization: Un/DoPack Identify regions to add white space SLIP 2007

13. 13 Congestion Localization Measurement SLIP 2007 Requirements: Applicable before and after placement, can integrate into Un/Dopack, can be easily displayed visually. Solution: Assign a congestion value to each CLB. Allows for localization before and after placement. Assigning to specific routing resources not practical before placement. Quality Measurement: Perform full place and route. Real congestion = Max tracks on each side of CLB. Compare to estimate.

14. 14 Quality Measurement: Fidelity VS Accuracy SLIP 2007 Previous work reports accuracy of estimate to actual peak channel widths. Does not report localization quality, or fidelity. Congestion estimation requires both accuracy and fidelity. Accuracy well studied. Therefore fidelity is the focus of this work. Fidelity can always be scaled to an accuracy heuristic. Good localization required to balance congestion. Fidelity = FPGA centric measurement. Higher Accuracy Higher Fidelity Poor LocalizationGood Localization Actual congestion from router

15. 15 Measuring Fidelity SLIP 2007 Linearly scale actual and real congestion maps so that min and max congestion of both maps are equal. Subtract difference between each CLB's congestion estimate and actual CLB's congestion value after place and route. % Error = Avg of absolute value of the differences / peak CLB congestion. Average absolute normalized error. M rows, M columns. E = Estimate, R = Real :

16. 16 Plot average cuts per partition size line of best fit: log T = p●log(G) + log(t) T =aG P p = Rent exponent. We will use this as our congestion value. Exploring heuristics: Local Rent Exponent SLIP 2007 log (# of CLBs) log (# of cuts)Window Size = 5

17. 17 Demo

24. 24 Exploring heuristics: Local Rent Exponent Benefit:  Characterizes wire length distribution. Downsides:  Requires a lot of data points.  Better for characterizing entire circuits.  Smaller window subject to anomylies.  Larger window loses locality of estimation.  Rate of change of cuts, not absolute value. SLIP 2007

25. 25 Exploring heuristics: Net cuts per region Rent exponent captures rate of change of cuts => wire length distribution. Absolute number of cuts may be better for locality. Example: region size of 3x3. Count number of nets crossing this boundary. SLIP 2007

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30. 30 Post Processing Heuristic #1: Cartesian Blending SLIP 2007 F0G0E0 A0B0C0 K0J0I0 F1 = (1-α)*F0 + α*(E0 + B0 + G0 + J0)/4 G1 = (1-α)*G0 + α*(F0 + C0 + H0 + K0)/4 H0 D0 L0 Blend Step 0

31. 31 Post Processing Heuristic #1: Cartesian Blending SLIP 2007 F2 = (1-α)*F1 + α*(E1 + B1 + G1 + J1)/4 G2 = (1-α)*G1 + α*(F1 + C1 + H1 + K1)/4 Blend Step 1 F1G1E1 A1B1C1 K1J1I1 H1 D1 L1

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39. 39 Exploring heuristics: Bounding Box Overlap Assign CLB value equal to number of bounding boxes it resides in. Zhuo et al. use this during every SA swap in VPR's placer, yielding avg of 7.1% channel width reduction. SLIP 2007

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41. 41 Exploring heuristics: Wire Length Per Area Expected wire-length of net = ½ perimeter bounding box SLIP 2007

42. 42 Probability of net routed at any given point in bounding box = expected length / bounding box area. Exploring heuristics: Bounding Box SLIP 2007

43. 43 ½ perimeter bounding box not realistic for high fan-out nets. extra pin factor = min(BBWidth, BBHeight)*max(0,num_pins – 3) expected wire length = 1/2BB + (extra pin factor)*α probability of wire = expected wire length / area Exploring heuristics: Wire Length Per Area SLIP 2007

50. 50 Blending helps spread probability distribution. Probability outside bounding box > 0. Exploring heuristics: Bounding Box SLIP 2007 p(wire) = 0 p(wire) > 0

51. 51 Post Processing Heuristic #2: Saturated Congestion Ideal routing solution would have no channel width constraint. Congestion maps of an architecture without a channel width constraint would have sharper peaks. Channel width constraint places a ceiling on wire density.  Forces routing in vicinity of ideal path. This ceiling and spreading of wire density can be emulated by saturating the congestion. SLIP 2007

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58. 58 Exploring Heuristics: Single Pass Route Pathfinder routes, calculates overuse, then reroutes. First routing attempt as congestion estimate.  Each CLB assigned congestion value based on max # of tracks used on each side of CLB. congestion = 4 SLIP 2007

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65. 65 Congestion Estimation Before Placement? All previous heuristics require spatial information. No spatial information available before placement. How can we accurately predict congestion localization without a placement? SLIP 2007

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67. 67 Cartesian blend: (needs placement info) Logical/Net blend: (Does not require placement info) Exploring Heuristics: Blending Pin Count SLIP 2007

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75. 75 Error Produced By Each Heuristic for MCNC 20 SLIP 2007 a.a.n.e.%

76. 76 Error Before and After Saturation and Blending SLIP 2007 a.a.n.e. %

77. 77 Speed VS Fidelity SLIP 2007 a.a.n.e.% Time (s)

78. 78 Can quickly and accurately locate regions of high congestion.  After placement Local Rent exponent Net cuts per region Bounding box overlap => improved => wire length per area Single pass route  Before placement Blending pin count => localize congestion before placement Post processing improve all heuristics. Compare fidelity instead of accuracy.  Necessary for balancing FPGA interconnect. Visual, tunable tool helpful for discovering / improving heuristics.  Journey as important as destination. Conclusion SLIP 2007

79. 79 Integrating into Un/DoPack. Congestion aware placement. Congestion aware clustering. Congestion estimation before clustering. Future Work SLIP 2007