SiliconAid Solutions, Inc. Confidential SAJE SiliconAid JTAG Environment Overview – Very Short

SiliconAid Solutions, Inc. Confidential SAJE JTAG Product Summary JTSJTVJTD SynthesisVerificationDebugger Generate P1687 JTAG Designs Verify BSDL and JTAG Design Provide JTAG Debug environment

SiliconAid Solutions, Inc. Confidential P1687 Activities YES – P1687 Exists and works SiAid is making significant investment Alpha software demos available Beta Software in development Partnering with key companies

SiliconAid Solutions, Inc. Confidential P1687 Simplified Basic Flow Wrap IP Wrap IP P1687 Synthesis P1687 Synthesis Pattern Conversion Pattern Conversion Generate Testbench Generate Testbench Simulate Wrap Existing IPs with 1500 wrapper and enhance for P1687 Automatically integrate wrapped IP, insert JTAG with P1687 compliant structures Verify JTAG and generate testbench to sim all test including IP patterns Convert Wrapped IP vectors into Chip level JTAG patterns

SiliconAid Solutions, Inc. Confidential The BIG PICTURE JTS JTV CHIP (JTD) Simulate Insert JTAG and 1687 Logic Generate Simulation and Chip Vectors Exhaustive semantic and compliance checking Verify JTAG and generate testbench to sim all test including IP patterns Matches Vectors by Vector: Simulation, CHIP, and BOARD Leverages Design data to drive and debug JTAG hardware BOARD Subset of Patterns for Board level support (SVF)

SiliconAid Solutions, Inc. Confidential Board SVF Debug Flow Generate Patterns Generate Patterns Simulate Verify JTAG and generate testbench to sim all test including IP patterns Debugger Board Test Board Test Fails

SiliconAid Solutions, Inc. Confidential JTVJTV STIL Vector file JTV - Typical ATE Flow No Verilog Netlist No Simulation Company A BSDL Your Specific Guidelines

SiliconAid Solutions, Inc. Confidential 1687 Network GUI Serial ATPG

SiliconAid Solutions, Inc. Confidential 1687 Board SVF Debug Flow 1687 ATPG 1687 ATPG Understands 1687 network and BSDL, Generates selected tests, SVF output Board Test Board Test Fails Board or ATE Debugger Board or ATE Debugger Interactive debugger – leverages design info into ATE and Board tests

SiliconAid Solutions, Inc. Confidential JTAG DEBUGGER TOOL (JTD) SiliconAid Solutions

SiliconAid Solutions, Inc. Confidential WHY JTD New Product Introduction/Evaluation Proto-typing pre-Silicon on Xilinx Boards Works in concert with ATE testers Debug capabilities to identify internal registers failing on TDO Tracks JTAG state machine on vector per vector basis Fast, easy, quick way to drive and observe standard JTAG signals Leverages JTV output to enhance debugging capability

SiliconAid Solutions, Inc. Confidential JTD Major Features Hardware Interface using USB 2.0 JTAG 5 pin connector Can drive evaluation board, Apps board, burn in board, ATE tester board, and more….. Compares expected values for TD0 Supports run till FAIL, STEP, etc.. Leverages patterns from JTV Supports external SVF patterns

SiliconAid Solutions, Inc. Confidential Initial JTD Window Debugger run and controls patterns Displays Fails on actual register Displays expected and actual data in waveforms Online Help and apps notes JTAG State Machine Viewer

SiliconAid Solutions, Inc. Confidential Debugger Window Fails Header Info Results Window log Window Command line Flow Control

SiliconAid Solutions, Inc. Confidential Register Viewer Failing bits are graphically displayed and bit descriptions pop up when clicked. Black – Expect 1 White – Expect 0 Red - Failed

SiliconAid Solutions, Inc. Confidential Waveform Viewer Capturing internal registers not accessible via pins on the device.

SiliconAid Solutions, Inc. Confidential JTAG State Machine Status Status is graphically displayed real time as the vectors are steps in the debugger window

SiliconAid Solutions, Inc. Confidential DEMO JTD USB 2.0 JTAG Signals TMS TDI TDO TCK TRST Apps Board

SiliconAid Solutions, Inc. Confidential What is JTV ?

SiliconAid Solutions, Inc. Confidential JTAG VERIFICATION TOOL (JTV) SiliconAid Solutions

SiliconAid Solutions, Inc. Confidential JTV - Purpose Verification support for JTAG providers –Focus is chip-level verification Provide an efficient means to –Insure correct JTAG functionality on first-pass silicon –Deliver a verified BSDL file for customer usage –Deliver high quality production test vectors –Diagnose fab-related pad or JTAG logic yield problems Goal is to –Eliminate customer BSDL and/or JTAG-related problems

SiliconAid Solutions, Inc. Confidential JTV Design Flow Diagram

SiliconAid Solutions, Inc. Confidential SAJE JTV simplified Flow BSDL User selectable test Testbench User selectable test Testbench Production Ready Patterns Production Ready Patterns Independent verification that BSDL matches your Design Verifies Design is IEEE & compliant Generates full suite of Production test vectors Generates verilog testbench & tests for verification Proven technology on hundreds of production designs More than 12 years + of success SAJE JTV Netlist with JTAG Netlist with JTAG JTAG Generation Legacy Designs Any 3rd Party tool Internally developed Any 3rd Party Simulator Any 3rd Party Simulator

SiliconAid Solutions, Inc. Confidential Board Companies Specific Benefits Screen for incoming BSDL Chip level ATE pattern Board Level targeted patterns for a chip No Verilog required Standardized test bench for all incoming design (if chip provider supplies verilog)

SiliconAid Solutions, Inc. Confidential Incoming BSDL and Verilog Process Flow Company A Company B Company C Company D JTVJTV Company X Specific Guidelines Company X Checker Release to Production

SiliconAid Solutions, Inc. Confidential JTVJTV STIL Vector file JTV - Typical ATE Flow No Verilog Netlist No Simulation Company A BSDL Company X Specific Guidelines

SiliconAid Solutions, Inc. Confidential Summary Simulation, ATE, and Board can have same patterns applied – Helps solve the NPF problems! Alpha 1687 Flow available JTD - Debugger works at chip level and plans to support board level in the future JTV is a mature product with 15+ years of continual history and usage and Chip verification and compliance checking Verifies BSDL matches design SVF Patterns will soon be portable to board test Tools be used in a custom or JTAG synthesis design flow Leverages Design data in ATE and Board Debug

SiliconAid Solutions, Inc. Confidential Jim Johnson : President phone: (512)

SiliconAid Solutions, Inc. Confidential