Gate Sizing by Mathematical Programming Prof. Shiyan Hu

2 Outline Overview Posynomial formulation Quadratic programming Combinational Circuit

3 Delay due to Wire/Gate Sizing R and C are functions of wire length l i, wire width w i and gate size g i Wire length l i : R  l i, C  l i Wire width w i : R  1/w i, C  w i Buffer/gate size g i : R  1/g i, C  g i Elmore delay is a function of RC Delay   R i C j, which is either  l i *l j or  w i /w j or  g i /g j, or their combinations

4 Mathematical Programming Quadratic programming Posynomial (positive polynomial) where all coefficients c i  0. Posynomial geometric programming Convex quadratic programming and posynomial programming can be solved in polynomial time using interior point methods

5 Approaches For wire sizing Fix wire width, then both R and C increases linearly with wire length. Therefore Elmore delay is a quadratic function of wire length For gate/buffer sizing The driving resistance decreases with gate width and input capacitance increases with gate width. Therefore Elmore delay is a posynomial function of gate width For combinational circuit Path delay can be expressed in terms of wire/gate delay and linear constraints. Therefore delay is a posynomial program

6 Outline Overview Quadratic programming Wire sizing Buffered wire sizing Posynomial formulation Lagrangian relaxation

7 Wire and Buffer Models

8 Wire Sizing Wire length variables l 1, l 2, …, l k corresponding to pre-selected wire width h 1, h 2, …, h n, and l 1 +l 2 +…+l k =L Monotone property h 1 >h 2 >…>h n

9 Elmore Delay Let c i =c(h i ), then

10 Quadratic Programming Minimize Subject to

11 Convex QP Due to special properties of matrix , it is positive definite The quadratic program is convex Convex QP is solvable in polynomial time using interior point methods.

12 Buffer Insertion and Wire Sizing There are m buffers of fixed sizes but variable location Between each pair of buffers/driver, there are n wire segments

13 Quadratic Programming Block matrix is positive definite The QP is convex and solvable in polynomial time Try different buffer numbers and sizes to find the optimal buffer location and wire sizing Minimize Subject to

14 Outline Overview Posynomial formulation Quadratic programming Combinational Circuit

15 Combinatorial Circuit Model Gate size variables x 1, x 2, x 3, wire width variables x 4, x 5, …, x 11 DriversLoads x6x6 x 11 x4x4 x7x7 x9x9 x 10 x2x2 x3x3 x8x8 x5x5 x1x1

16 Path Delay Express path delay in terms of component delay Arrival time a i for component i Delay D i for component i Constant number of constraints for each component 1 a1a1 a2a2 a3a3 D3D3 a4a4 D4D4

17 Wire/Gate Sizing Power/area minimization under delay constraints: This is a typical posynomial geometric programming problem, and can be solved in polynomial time or by Lagrangian relaxation

18 Reference for Math Programming J. P. Fishburn and A. E. Dunlop, TILOS: A posynomial programming approach to transistor sizing, ICCAD 1985, pp N. Menezes, R. Baldick and L. T. Pileggi, A sequential quadratic programming approach to concurrent gate and wire sizing, DAC 1995, C. C. N. Chu and D. F. Wong, A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing, IEEE Trans. on CAD, June 1999, pp C.-P. Chen, C. C. N. Chu and D. F. Wong, Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation, IEEE Trans. On CAD, July 1999, C. C. N. Chu and D. F. Wong, An efficient and optimal algorithm for simultaneous buffer and wire sizing, IEEE Trans. on CAD, Sept. 1999, pp