1. Circuit Retiming with Interconnect Delay CUHK CSE CAD Group Meeting One Evangeline Young Aug 19, 2003

2. Circuit Retiming Given a circuit, we want to relocate the registers to achieve a better clock period. Registers Retiming Clock period = 3 units Clock period = 2 units

3. Circuit Retiming In order to maintain the functionality of the circuit, registers can only be moved in certain ways: Retiming

4. Circuit Retiming Given a circuit, how should we place the registers to minimize the clock period?

5. Traditional Approach This retiming problem is firstly introduced in the following classical paper: “Retiming Synchronous Circuitry”, Charles E. Leiserson and James B. Saxe, Algorithmica, 6:5-35, 1991 Only gate delay was considered. Three methods are proposed. One of them solves the problem by mixed integer linear programming (MILP).

6. Traditional Approach Notations: d(v) is the delay of node v. w(e) is the original no. of registers on edge e. c is the clock period that we want to check if it is feasible. r(v) is the retiming value of node v, i.e., the no. of registers moved from the output to the input of node v. (r(v) is what we want to find.) s(v) is the longest delay from a register connected directly to node v to the output of v.

7. Traditional Approach More about s(v)… v s(v) is the delay from point A to B, including the delay of v. A B

8. Traditional Approach Integer Linear Program: d(v)  s(v)for all node v (1) s(v)  c for all node v (2) r(u)  r(v)  w(e)for all edge e(u,v)(3) s(u) – s(v)  -d(v)wherever e(u,v) s.t. r(u) - r(v) = w(e)(4)

9. Traditional Approach Write R(v) as r(v) + s(v)/c The ILP can be written as an MILP: r(v) – R(v)  -d(v)/cfor all node v (1) R(v) – r(v)  1 for all node v (2) r(u)  r(v)  w(e)for all edge e(u,v)(3) R(u) – R(v)  w(e)-d(v)/cfor all edge e(u,v) (4) The above set of difference constraints can be solved in polynomial time, though it consists of both integer and real variables.

10. Traditional Approach Use binary search to find the optimal clock: T 0 = 0 T 1 = e 10 // a large no. Repeat c = (T 0 + T 1 )/2 Check if c is a feasible clock period by solving the MILP. If success, T 1 = c; otherwise, T 0 = c. Until success and (T 1 - T 0 )/T 1 < ε

11. Retiming with Interconnect Delay We consider clock period minimization. Retiming has been studied and applied extensively at logic synthesis. However, most previous retiming algorithms ignore interconnect delay. Interconnect delay should be considered for high performance circuits in DSM design. This solution is going to be presented in the upcoming ICCAD 2003.

12. Retiming with Interconnect Delay We assume that wire delay is directly proportional to its length. This assumption is reasonable: For short wires, the quadratic component of a wire delay is significantly smaller than its linear component. For long wires, buffer insertion can be done.

13. Retiming with Interconnect Delay

14. Now, a retiming solution needs to specify: the retiming label r(v) for each node v. the positions of the registers on each edge. The positions of the registers on the edges are important as there are interconnect delay. Retiming r( ) = 0 r( ) = -1

15. Our Contributions Optimal algorithm: O(|V||E| log |V| + |V| 2 log 2 |V|) time per iteration. Near-optimal algorithm: Only 0.13% larger than the optimal on average. O(|V b ||E| + |V b ||E h |) time per iteration, e.g., a circuit with 16.1K gates and 28.6K wires can be retimed in 44.32s by a 1.8GHz PIII PC. Based on an optimal algorithm handling interconnect delay only, i.e., no gate delay.

16. Optimal Approach Rewrite the ILP on p.8 as follows: d(v)  s(v)for all node v (1) s(v)  c for all node v (2) r(u)  r(v)  w(e)for all edge e(u,v)(3) s(v) ≥ s(u) + d(e) + d(v) - c(r(v) - r(u) + w(e)) for all edge e(u,v) (4)

17. Optimal Approach Similarly, write R(v) as r(v) + s(v)/c: r(v) – R(v)  -d(v)/cfor all node v (1) R(v) – r(v)  1 for all node v (2) r(u)  r(v)  w(e)for all edge e(u,v)(3) R(u) – R(v)  w(e) - d(v)/c - d(e)/c for all edge e(u,v) (4) Again, the above set of constraints can be solved in polynomial time, though the runtime is quite long.

18. Optimal Approach Circuit |V||E|c opt Runtime (s) s1488655140518.855.62 s1494649141120.784.37 s32711574270710.2433.70 s33301791289027.0543.14 s33841687278224.1625.19 s48632344409323.5887.75 s53782781426127.25138.68 s66693082539922.96177.59 s92345599800542.73512.86 s1320779531130272.341161.07 s1585097741379467.821545.59 s35932160672859029.548644.27 s38417221813213536.527680.79 s385841925533010>15000

19. Near Optimal Approach Transform the original graph G by splitting each node v (represents a gate) into a pair of nodes v 1 and v 2 connected by an edge with delay d(v). v v1v1 v2v2 delay = d(v) delay = 0

20. Near Optimal Approach After representing each gate by a wire, we can find an optimal retiming solution S for the transformed circuit G 1. (We will show how to find the optimal solution with no gate delay.) The clock period of S will be a lower bound L for the optimal solution T opt of G. From S, we can obtain a feasible retiming solution for the original circuit G.

21. Near Optimal Approach Registers retimed into a wire representing a gate v will be moved backward to the input edges or forward to the output edges depending on their distances from v 1 and v 2. Linear programming is used to determine the positions of the registers on each edge after this relocation step to minimize the clock period considering both gate and wire delay. v1v1 v2v2

22. Near Optimal Approach It is now the problem of solving the retiming problem optimally assuming that gate delay is zero. When there is no gate delay, the set of constraints on p.17 becomes: r(v) – R(v)  0for all node v (1) R(v) – r(v)  1 for all node v (2) r(u)  r(v)  w(e)for all edge e(u,v)(3) R(u) – R(v)  w(e)-d(e)/cfor all edge e(u,v) (4)

23. Near Optimal Approach Lemma 1: Given R(v) for all node v that satisfy constraint (4), we can obtain a solution to constraint (1)-(4) by setting r(v) = trunc(R(v)) Given Lemma 1, we only need to solve constraint (4): R(u) – R(v)  w(e)-d(e)/c for all edge e(u,v). Consider the input graph G(V,E) such that the weight of each edge e(u,v) is -w(e)+d(e)/c.

24. Near Optimal Approach There is a solution to constraint (4) iff G has no positive cycles. Positive cycle detection in G can be achieved by positive cycle detection in a smaller graph H(V b,E h ) constructed from G. This technique can be applied in other positive cycle detection problems, not necessarily in circuit retiming. After solving R(v), we can find r(v) and s(v) for all node v.

25. Near Optimal Approach After the binary search, we can find the optimal clock and the corresponding r(v) and s(v) for all node v. Then, we can place the registers accordingly: uv c Other registers are placed right in front of v. c - s(u) Assume that r(v)-r(u)+w(e) = 4

26. Near Optimal Approach First, assuming that gate delay is zero. Binary search to find the minimum feasible clock period c To test the feasibility of a fixed c: Transforming to a positive cycle detection problem on a reduced graph Can be solved by a single-source longest-path algorithm

27. Results Circuit c opt T opt (s) s148818.825.62 s149420.784.37 s327110.2433.70 s333027.0543.14 s338424.1625.19 s486323.5887.75 s537827.25138.68 s666922.96177.59 s923442.73512.86 s1320772.341161.07 s1585067.821545.59 s3593229.548644.27 s3841736.527680.79 s38584>15000 c near opt 18.85 20.78 10.24 27.05 24.21 23.58 27.27 23.07 42.73 72.34 67.82 29.59 36.53 T near opt (s) 0.28 0.25 1.09 0.50 0.74 3.12 1.16 1.91 4.08 8.11 24.02 61.25 83.56 445.63 94.26

28. Future Directions Consider a more accurate modeling for the interconnect delay, e.g., use Elmore delay. How to map the retiming solution to the floorplanning or placement solution? Registers are large and take up silicon resources. How to consider fan-out capacitance with interconnect delay?