1. Chapter 2 Interconnect Analysis Delay Modeling
Prof. Lei He
Electrical Engineering Department
University of California, Los Angeles
URL: eda.ee.ucla.edu

2. Outline Delay models RC tree Elmore delay (First Order) Gate delay
ECE902 VLSI Interconnect
Outline
Delay models
RC tree Elmore delay (First Order)
Second Order Analysis (S2P algorithm)
Gate delay
Prepared by Lei He

3. Input-to-Output Propagation Delay
The circuit delay in VLSI circuits consists of two components:
The 50% propagation delay of the driving gates (known as the gate delay)
The delay of electrical signals through the wires (known as the interconnect delay)

4. Lumped vs Distributed Interconnect Model
ECE902 VLSI Interconnect
Lumped vs Distributed Interconnect Model
Lumped
Distributed R C r c
How to analyze the delay for each model?
Prepared by Lei He

5. Lumped RC Model R
v(t)
u(t) C
Impulse response and step response of a lumped RC circuit

6. Analysis of Lumped RC Model
ECE902 VLSI Interconnect R C
S-domain ckt equation (current equation)
Frequency domain response for step-input
Frequency domain response for impulse
match initial state: v0
v0(1-eRC/T)
Time domain response
for step-input:
Time domain response
for impulse:
Prepared by Lei He

7. 50% Delay for lumped RC model
V(t) 1v 1
0.5
50% delay
How about more complex circuits?

8. Distributed RC-Tree The network has a single input node
ECE902 VLSI Interconnect
Distributed RC-Tree R1 C1 s R2 C2 R4 C4 C3 R3 Ci Ri 1 2 3 4 i
The network has a single input node
All capacitors between node and ground
The network does not contain any resistive loop
Prepared by Lei He

9. ECE902 VLSI Interconnect
RC-tree Property R1 C1 s R2 C2 R4 C4 C3 R3 Ci Ri 1 2 3 4 i
Unique resistive path between the source node s and any other node i of the network  path resistance Rii
Example: R44=R1+R3+R4
Prepared by Lei He

10. RC-tree Property Extended to shared path resistance Rik:
ECE902 VLSI Interconnect
RC-tree Property R1 C1 s R2 C2 R4 C4 C3 R3 Ci Ri 1 2 3 4 i
Extended to shared path resistance Rik:
Example: Ri4=R1+R3
Ri2=R1
Prepared by Lei He

11. The Elmore delay at node i is:
ECE902 VLSI Interconnect
Elmore Delay
Assuming:
Each node is initially discharged to ground
A step input is applied at time t=0 at node s
The Elmore delay at node i is:
Theorem: The Elmore delay is equivalent to the first-order time constant of the network
Proven acceptable approximation of the real delay
Powerful mechanism for a quick estimate
Prepared by Lei He

12. Example Elmore delay at node i is 2 R2 R1 C2 4 1 s R4 R3 C4 C1 3 Ri C3
ECE902 VLSI Interconnect
Example R1 C1 s R2 C2 R4 C4 C3 R3 Ci Ri 1 2 3 4 i
Elmore delay at node i is
Prepared by Lei He

13. Interpretation of Elmore Delay
ECE902 VLSI Interconnect
Interpretation of Elmore Delay
median
of h(t)
(T50%)
h(t) = impulse response
H(t) = step response
Definition
h(t) = impulse response
TD = mean of h(t) =
Interpretation
H(t) = output response (step process)
h(t) = rate of change of H(t)
T50%= median of h(t)
Elmore delay approximates the median of h(t) by the mean of h(t)
Prepared by Lei He

14. Elmore Delay Approximation

15. RC-chain (or ladder) Special case:
ECE902 VLSI Interconnect
RC-chain (or ladder)
Special case:
Shared-path resistance path resistance R1 C1 R2 C2 RN CN
Vin VN
Prepared by Lei He

16. RC-Chain Delay Delay of wire is quadratic function of its length
ECE902 VLSI Interconnect
RC-Chain Delay R C R C R C
Vin VN
R=r · L/N
C=c·L/N
Delay of wire is quadratic function of its length
Delay of distributed rc-line is half of lumped RC
Prepared by Lei He

17. Outline Delay models RC tree Elmore delay (First Order) Gate delay
ECE902 VLSI Interconnect
Outline
Delay models
RC tree Elmore delay (First Order)
Second Order Analysis (S2P algorithm)
Gate delay
Prepared by Lei He 17

18. Stable 2-Pole RC delay calculation (S2P)
The Elmore delay is the metric of choice for performance-driven design applications due to its simple, explicit form and ease with which sensitivity information can be calculated
However, for deep submicron technologies (DSM), the accuracy of the Elmore delay is insufficient

19. Moments of H(s)
Moments of H(s) are coefficients of the Taylor’s Expansion of H(s) about s=0

20. Driving Point Admittance
Let Y(s) be an driving point admittance function of a general RC circuit. Consider its representation in terms poles and residues
where q is the exact order of the circuit
Moments of Y(s) can be written as:

21. S2P Algorithm Compute m1, m2, m3 and m4 for Y(s)
Find the two poles at the driving point admittance as follows:
To match the voltage moments at the response nodes, choose
and the S2P approximation is then expressed as:
Note that m0* and m1* are the moments of H(s). m0* is the Elmore delay.

22. S2P Vs. Elmore Delay

23. Outline Delay models RC tree Elmore delay (First Order) Gate delay
ECE902 VLSI Interconnect
Outline
Delay models
RC tree Elmore delay (First Order)
Second Order Analysis (S2P algorithm)
Gate delay
Prepared by Lei He 23

24. Gate Delay and Output Transition Time
The gate delay and the output transition time are functions of both input slew and the output load

25. General Model of a Gate

26. Definitions Output Transition Time Gate Delay Vin Vout Time 90% 10%W p n C M
out
Cdiff
Cload
Vin
Vout
Cout

27. Output Response for Different Loads

28. Output Transition Time
Input Transition Time (s)
Output Transition time (s)
10-10
CLoad (F)
10-14
Output transition time as a function of input transition time and output load

29. ASIC Cell Delay Model
Three approaches for gate propagation delay computation are based on:
Delay look-up tables
K-factor approximation
Effective capacitance
Delay look-up table is currently in wide use especially in the ASIC design flow
Effective capacitance promises to be more accurate when the load is not purely capacitive

30. Table Look-Up Method
115pS
What is the delay when Cload is 505f F and Tin is 90pS?

31. K-factor Approximation
Input Transition Time (s)
Output Transition time (s)
10-10
CLoad (F)
10-14
We can fit the output transition time v.s. input transition time and output load as a polynomial function, e.g.
A similar equation gives the gate delay

32. One Dimensional Table
Linear model

33. Two Dimensional Table D1 D4 D3 D2
Quadratic model

34. Second-order RC-p Model
Using Taylor Expansion around s = 0

35. Second-order RC-p Model (Cont’d)
This equation requires creation of a four-dimensional table to achieve high accuracy
This is however costly in terms of memory space and computational requirements

36. Effective Capacitance Approach
The “Effective Capacitance” approach attempts to find a single capacitance value that can be replaced instead of the RC-p load such that both circuits behave similarly during transition

37. Output Response for Effective Capacitance

38. Effective Capacitance (Cont’d)

39. Effective Capacitance (Cont’d)
0<k<1
Because of the shielding effect of the interconnect resistance , the driver will only “see” a portion of the far-end capacitance C2 Rp
k = 1
Rp ∞
k = 0

40. Effective Capacitance for Different Resistive Shielding

41. Macy’s Approach
Assumption: If two circuits have the same loads and output transition times, then their effective capacitances are the same
=> the effective capacitance is only a function of the output transition time and the load

42. Macy’s Iterative Solution
Compute a from C1 and C2
Choose an initial value for Ceff
Compute Tout for the given Ceff and Tin
Compute b
Compute g from a and b
Find new Ceff
Go to step 3 until Ceff converges

43. Summary Delay model Elmore delay
Gate delay: look-up table, k-factor approximation, effective capacitance 43

44. References
R. Macys and S. McCormick, “A New Algorithm for Computing the “Effective Capacitance” in Deep Sub-micron Circuits”, Custom Integrated Circuits Conference 1998, pp
J. Qian, S. Pullela, and L. T. Pileggi, "Modeling the "effective capacitance" for the RC interconnect of CMOS gates," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, pp , Dec
Jason Cong , Lei He , Cheng-Kok Koh , Patrick H. Madden, Performance optimization of VLSI interconnect layout, Integration, the VLSI Journal, v.21 n.1-2, p.1-94, Nov (Section )
W. C. Elmore, “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers”, Journal of Applied Physics, 1948.
Jorge Rubinstein, and etc. “Signal Delay in RC Tree Networks”, TCAD'83
Emrah Acar, Altan Odabasioglu, Mustafa Celik, and Lawrence T. Pileggi “S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric”. In Proceedings of the Ninth Great Lakes Symposium on VLSI(GLS '99). 44