Probabilistic Testability Analysis Aditya Newalkar.

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Presentation transcript:

Probabilistic Testability Analysis Aditya Newalkar

Characteristics of a testability analysis program Goal is not to generate test vectors themselves but to aid the generation of test vectors Linear complexity Predicts test coverage Handles the reconvergent fanouts

Our goals Find the probabilistic testability of all the stuck at faults Find 10% of the hardest to detect faults

Strategy The 1-observability of (signal) A at (output) F is a measure of how many patterns can detect a single stuck-at-0 fault of A at F, and vice versa for 0-observability [Brg89]. P(D/0) = P(D=1)*0-observability of signal D Find the 0-observability and 1-controllability of all the signals, Take the product to find the probability of s- a-0 fault. P(D/1) = P(D=0)*1-observability of signal D

Reconvergent fanouts Signals are no longer independent Testability measures cannot be calculated independently Causes significant error in the measurement

Graph model of netlist Netlist is viewed as a directed simple graph Each gate is a node Each net is an arc (directed edge) The gate node is connected to one output node (“SRC” node) The gate node is connected to two or more input nodes (“DEST” nodes) “SRC” nodes are connected to “DEST” nodes of the next gate The direction of the arc is always “SRC” to “DEST”

Algorithm for calculating Controllability While indegreeOf(P) > 0 InPinControlArray[i] = controllability of incoming edges of P i++ End While If (P == Primary Input) then Return 0.5 If (P == LogicGateType) then Calculate controllability of the output from the array InPinControlArray Return controllability Else Add all the controllability values in the array InPinControlArray Return controllability End if

Result and Discussion C Coverage99 % Hardest Fault (s-a-0)6E20 Hardest Fault (s-a-1)7A6 Minimum 1-Observability Minimum 0-Observability