1 Final Presentation Project A – Spring 2009 High Speed Signal Processing Board Design Student: Nir Malka Lior Rom Instructor: Mike Sumszyk Duration: 1 Semester

2 Table of Contents Main Goal Project overview Project Implementation Board specifications Orcad Schematics High Speed VHDL Modules Description

3 Main Goal Design a high speed analog to digital daughter board which interfaces to Altera DE3. Design a high speed analog to digital daughter board which interfaces to Altera DE3.

4 Project Overview Designing a new daughter board, which will interface to Altera DE3, and will be able to perform DAC and ADC sampling, at HS frequencies. Preparing a manufacturing file, containing Orcad schematics, and main VHDL blocks.

5 Project Implementation (Top Level) Sample Real Time Digital Processing (DE3) Reconstruction Analog Input Analog Output

6 Project Implementation (Block Level) High Speed signal processing Board Analog Input Circuit ADC Analog Output Circuit DAC DE3 (Digital Processing) Analog signal Digital signal HSTC RGB Signal 2 Ch analog Signal

7 Brief Description of AD Main Features: Diff Input voltage: 1.25 Vp-p 10 Bits Conversion Rate: up to 300 MSPS LVDS outputs

8 Brief Description of AD9780 Dual channel Up to 500 Msps Differential analog current outputs LVDS inputs

9 Board Specifications (Power Supply) DC voltage supply: – Main DC power source from external DC supplier of 8.5V, into voltage regulators which output: AVDD 1.8V, AVDD3.3 DRVDD 1.8V, DVDD3.3 DC current consumption – ADC Supply Currents I AVDD < 203 mA – DAC Supply Currents I AVDD < 58mA

10 Board Specifications (inputs) ADC Analog input signal: – Differential input voltage range: 1.25 Vp-p – Analog Input bandwidth: 70 MHz – Protection from Input over voltage (ESD) ADC External clock input – Clock generator through SMA connector – Min conversion Rate 40 MSPS, 50% duty cycle – Differential Input voltage range < 6 Vp-p

11 Board Specifications (outputs) 4 Analog output signals – 2 channels with sample rate of up to 500 Msps. – Output compliance range: -1V to 1V – 2 Aux channels, can be used to remove the DC offset voltage.

12 Board Specifications (Placing) AUX 1 AUX 2 8.5cm 10cm CLK R G B DACI 6.1cm PS DACQ AUX2AUX1

13 Board Specifications (PCB Stack)

14 LVDS SIGNALSANALOG SIGNALS D-GNDA-GND FR4 DIGITAL VCC FR4 ANALOG VCC FR4 D-GND FR4 DIGITAL SIGNALS Board Specifications (PCB Stack)

15 Orcad schematics Orcad Schematics Tango Net-list BOM

16 High Speed (Special notes to the Editor) High Speed Design guidelinesDesign

17 VHDL Modules Description DE3 DATA TO DAC DATA FROM ADC CONFIGURATION USER INTERFACE 50Mhz DE3 OSCILLATOR

18 VHDL Modules Description (ADC Interface) ENTITY ADC_INTERFACE IS port ( DB : IN STD_LOGIC_VECTOR(7 downto 0); DG : IN STD_LOGIC_VECTOR(7 downto 0); DR : IN STD_LOGIC_VECTOR(7 downto 0); B : OUT STD_LOGIC_VECTOR(7 downto 0); G : OUT STD_LOGIC_VECTOR(7 downto 0); R : OUT STD_LOGIC_VECTOR(7 downto 0) ); END ADC_INTERFACE;

19 VHDL Modules Description (DAC Interface) ENTITY DAC_INTERFACE IS port ( CLK1 : IN STD_LOGIC; CLK180 : IN STD_LOGIC; CLK2 : IN STD_LOGIC; GB : IN STD_LOGIC_VECTOR(23 downto 12); RG : IN STD_LOGIC_VECTOR(11 downto 0); CLK : OUT STD_LOGIC; OUTPUT : OUT STD_LOGIC_VECTOR(11 downto 0) ); END DAC_INTERFACE;

20 VHDL Modules Description (SPI Interface) ENTITY spi_interface IS port ( RESET_AD : IN STD_LOGIC; CSBAD : IN STD_LOGIC; SCLK : IN STD_LOGIC; CSBDA : IN STD_LOGIC; RESET_DA : IN STD_LOGIC; select_mux : IN STD_LOGIC_VECTOR(1 downto 0); CSB2AD : OUT STD_LOGIC; RESET2AD : OUT STD_LOGIC; SDIO : OUT STD_LOGIC; CSB2DA : OUT STD_LOGIC; RESET2DA : OUT STD_LOGIC ); END spi_interface;

21 VHDL Modules Description (Clock Distributer) ENTITY CLOCK _DISTRIBUTER IS port ( LVDS_CLK : IN STD_LOGIC; CLK1 : OUT STD_LOGIC; CLK180 : OUT STD_LOGIC; CLK2 : OUT STD_LOGIC ); END CLOCK _DISTRIBUTER;

22 VHDL Modules Description (Data path)

23 Sample 1 Sample 2

24 VHDL Modules Description (SPI)

25 RESET_ADRESET_DA MUX_SEL CONFIGURATION CSB_DA CSB_AD

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28 Lookup table Mux_selectDescription 00Enable DDR mode for ADC 01OverRange disable for ADC 10Timing adjust for DAC 11Data control DAC- switch from two’s complement to binary