1. Development System using Altium Designer Supervisor : Ina Rivkin Performed by: Fared Ghanayim Jihad Zahdeh Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab Midterm Presentation One Semester Project “Spring 2007”

2. Agenda Project Goals. Project Goals. Design block Diagram. Design block Diagram. Schematic building Schematic building Schedule Schedule

3. Project Goals Building a design using Altium Designer Building a design using Altium Designer Knowing different features of Altium Designer Knowing different features of Altium Designer Building the Schematic Diagram Building the Schematic Diagram Using VHDL for implementing one of the schematic units and Simulation and Synthesis. Using VHDL for implementing one of the schematic units and Simulation and Synthesis. Embedded code. Embedded code. Signal Integrity. Signal Integrity.

4. Design Block Diagram

5. Schematic Building Creating a new FPGA Project

6. Major units we used in schematics and their Libraries Name in Library LibraryComponent TSK51A_D FPGA ProcessorsMicroprocessor SRAM_0 FPGA NanoBorad port plugin SRAM LCD FPGA NanoBorad port Plugin LCD DipSwitch Switches Soft Nexus-Chain Connector NEXUS_JTAG_CONNECTOR FPGA NanoBorad port Plugin Nexus Jtag port, connecter CLK_BRD FPGA NanoBorad port Plugin Clock LCD16X2A FPGA Peripherals LCD Controller (OR, And,..) FPGA Generic Logical units

7. Top Level Design Timing JTAG Processor LCD Controller LCD SRAM Memory Controller

8. SRAM Description OF SRAM PINS: Data I/O Enable Address Write Enable Output Enable Upper Bit Lower Bit

9. Top Level Design Diagram FPGA Microprocessor Block

10. CPU Diagram with internal Mem. Microprocessor ROM Input Output Ports Clock and Reset ports

11. Top Level Design Diagram Top Level Design Diagram Memory Controller Block

12. Memory Controller Implementation in VHDL library IEEE; use IEEE.Std_Logic_1164.all; entity Mem_cont is port ( sel : in std_logic; inp : in std_logic_vector(15 downto 0); outp : out std_logic_vector(15 downto 0); io : inout std_logic_vector(15 downto 0); IMEM : in std_logic_vector(7 downto 0); IADDR : in std_logic_vector(15 downto 0); OADDR : out std_logic_vector(18 downto 0); OCS : out std_logic; OUB : out std_logic; OLB : out std_logic ); end Mem_cont; -------------------------------------------------------------------------------- architecture strc of Mem_cont is begin outp 'Z'); io 'Z'); OADDR(0) <= IADDR(0); OADDR(1) <= IADDR(1); OADDR(2) <= IADDR(2); OADDR(3) <= IADDR(3); OADDR(4) <= IADDR(4); OADDR(5) <= IADDR(5); OADDR(6) <= IADDR(6); OADDR(7) <= IADDR(7); OADDR(8) <= IADDR(8); OADDR(9) <= IADDR(9); OADDR(10) <= IADDR(10); OADDR(11) <= IADDR(11); OADDR(12) <= IADDR(12); OADDR(13) <= IADDR(13); OADDR(14) <= IADDR(14); OADDR(15) <= IADDR(15); OLB <= IMEM(0); OUB <= not IMEM(0); OCS <= '1'; OADDR(16) <= IMEM(1); OADDR(17) <= IMEM(2); OADDR(18) <= IMEM(3); end strc ;

13. Schedule 14/6 Presenting midterm Presentation. 14/6 Presenting midterm Presentation. 15/6 – 29/6 Embedded code and compilation 15/6 – 29/6 Embedded code and compilation 30/6 – 7/7 simulation and synthesis. 30/6 – 7/7 simulation and synthesis. 8/7 – 15/7 Signal Integrity. 8/7 – 15/7 Signal Integrity. 1/8 Final Presentation. 1/8 Final Presentation.