Digital Design – Physical Implementation Chapter 7 - Physical Implementation.

Slides:

Advertisements

Similar presentations

CT455: Computer Organization Logic gate

Advertisements

Digital Logic Design Week 7 Encoders, Decoders, Multiplexers, Demuxes.

Digital Design Copyright © 2006 Frank Vahid 1 FPGA Internals: Lookup Tables (LUTs) Basic idea: Memory can implement combinational logic –e.g., 2-address.

©2004 Brooks/Cole FIGURES FOR CHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES Click the mouse to move to the next page. Use the ESC key.

Physical Implementation 1)Manufactured Integrated Circuit (IC) Technologies 2)Programmable IC Technology 3)Other Technologies Other Technologies 1. Off-The-Shelf.

1 Other Technologies Off-the-shelf logic (SSI) IC –Logic IC has a few gates, connected to IC's pins Known as Small Scale Integration (SSI) –Popular logic.

Programmable logic and FPGA

FIGURE 7-24 Memory map for the 8088 interface in Figure 7-22 and decoder in Figure The 64K SRAM is mapped to the address range E0000H to EFFFFH.

Multiplexers, Decoders, and Programmable Logic Devices

Combinational Logic1 DIGITAL LOGIC DESIGN by Dr. Fenghui Yao Tennessee State University Department of Computer Science Nashville, TN.

ECE 331 – Digital System Design Tristate Buffers, Read-Only Memories and Programmable Logic Devices (Lecture #16) The slides included herein were taken.

Physical Implementation 1)Manufactured Integrated Circuit (IC) Technologies 2)Programmable IC Technology 3)Other Technologies Manufactured IC Technologies.

Chapter 7: Physical Implementation

1 Introduction A digital circuit design is just an idea, perhaps drawn on paper We eventually need to implement the circuit on a physical device –How do.

Programmable Array Logic (PAL) Fixed OR array programmable AND array Fixed OR array programmable AND array Easy to program Easy to program Poor flexibility.

Digital Design - Combinational Logic Design Chapter 2 - Combinational Logic Design.

Figure to-1 Multiplexer and Switch Analog

EE 261 – Introduction to Logic Circuits Module #8 Page 1 EE 261 – Introduction to Logic Circuits Module #8 – Programmable Logic & Memory Topics A.Programmable.

Chapter 4 Programmable Logic Devices: CPLDs with VHDL Design Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights.

1 CHAPTER 4: PART I ARITHMETIC FOR COMPUTERS. 2 The MIPS ALU We’ll be working with the MIPS instruction set architecture –similar to other architectures.

Digital Computer Concept and Practice Copyright ©2012 by Jaejin Lee Logic Circuits I.

Transistors and Logic Circuits. Transistor control voltage in voltage out control high allows current to flow -- switch is closed (on) control low stops.

Microprocessor Address Decoding.

Logic Gates How Boolean logic is implemented. Transistors used as switches to implement Boolean logic: ANDOR Logic with Transistors.

Unit 9 Multiplexers, Decoders, and Programmable Logic Devices

Programmable Implementation Technologies Digital Logic Design Instructor: Kasım Sinan YILDIRIM.

Digital Design Copyright Frank Vahid 1 Digital Design Chapter 7: Physical Implementation Slides to accompany the textbook Digital Design, First Edition,

Memory and Programmable Logic Memory device: Device to which binary information is transferred for storage, and from which information is available for.

Programmable Logic Devices

1 Lecture #10 EGR 277 – Digital Logic Multiplexers (Data Selectors) A multiplexer (MUX) is a device that allows several low-speed signals to be sent over.

CHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES

Chapter 4 Programmable Logic Devices: CPLDs with VHDL Design Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights.

0/13 Introduction to Programmable Logic Devices Aleksandra Kovacevic Veljko Milutinovic

Basic Sequential Components CT101 – Computing Systems Organization.

4. Computer Maths and Logic 4.2 Boolean Logic Logic Circuits.

M.Mohajjel. Why? TTM (Time-to-market) Prototyping Reconfigurable and Custom Computing 2Digital System Design.

Digital Logic Structures: Chapter 3 COMP 2610 Dr. James Money COMP

ESS | FPGA for Dummies | | Maurizio Donna FPGA for Dummies Basic FPGA architecture.

Programmable logic devices. CS Digital LogicProgrammable Logic Device2 Outline PLAs PALs ROMs.

Chapter 3 Digital Logic Structures

PLDS Mohammed Anvar P.K AP/ECE Al-Ameen Engineering College.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas.

Programmable Logic Devices

Gunjeet Kaur Dronacharya Group of Institutions. Outline Introduction Random-Access Memory Memory Decoding Error Detection and Correction Programmable.

Programmable Logic Devices

This chapter in the book includes: Objectives Study Guide

ETE Digital Electronics

Chapter 7: Physical Implementation

Sequential Logic Design

Transistors and Logic Circuits

This chapter in the book includes: Objectives Study Guide

From Silicon to Microelectronics Yahya Lakys EE & CE 200 Fall 2014

Digital Signals Digital Signals have two basic states:

Dr. Clincy Professor of CS

This chapter in the book includes: Objectives Study Guide

Programmable Logic Devices: CPLDs and FPGAs with VHDL Design

Dr. Clincy Professor of CS

Computer Science 210 Computer Organization

FIGURE 7.1 Conventional and array logic diagrams for OR gate

Physical Implementation Manufactured IC Technologies

Dr. Clincy Professor of CS

Dr. Clincy Professor of CS

13 Digital Logic Circuits.

EEE2243 Digital System Design Chapter 9: Advanced Topic: Physical Implementation by Muhazam Mustapha extracted from Frank Vahid’s slides, May 2012.

Digital Logic Experiment

FIGURE 5-1 MOS Transistor, Symbols, and Switch Models

Physical Implementation

Digital Logic Design Basics Combinational Circuits Sequential Circuits.

Programmable logic and FPGA

Presentation transcript:

Digital Design – Physical Implementation Chapter 7 - Physical Implementation

2 Digital Design Physical Implementation Figure 7.1 How do we get from A to B?

3 Digital Design Physical Implementation Figure 7.2 Custom IC design.

4 Digital Design Physical Implementation Figure 7.3 Gate array technology -- note: real gate arrays have thousands of gates, not just a few.

5 Digital Design Physical Implementation Figure 7.4 Half-adder on a gate array.

6 Digital Design Physical Implementation Figure 7.5 Standard cell technology.

7 Digital Design Physical Implementation Figure 7.6 Half-adder using standard cells.

8 Digital Design Physical Implementation Figure 7.7 Implementing an AND/OR circuit using NANDs only -- half-adder sum example.

9 Digital Design Physical Implementation Figure 7.8 Converting a one-level AND circuit to NAND.

10 Digital Design Physical Implementation Figure 7.9 FPGA chips.

11 Digital Design Physical Implementation Figure 7.10 Implementing logic functions using a memory: (a) 2-input function truth table, (b) corresponding memory contents and connections, (c) the proper output appears for the given input values, (d) two functions having the same two inputs, (e) memory contents for the two functions.

12 Digital Design Physical Implementation Figure 7.11 Lookup table implementation.

13 Digital Design Physical Implementation Figure 7.12 Partitioning a circuit onto two lookup tables.

14 Digital Design Physical Implementation Figure 7.13 Partitioning a circuit onto two lookup tables. Italicized bits are unused.

15 Digital Design Physical Implementation Figure 7.14 Implementing a 2x4 decoder onto two 3-input 2-output lookup tables. Italicized bits are unused.

16 Digital Design Physical Implementation Figure 7.15 A partial FPGA that includes a switch matrix (left), and the switch matrix’s internals showing two 4x1 muxes controlled by two 2-bit registers (right).

17 Digital Design Physical Implementation Figure 7.16 Implementing a 2x4 decoder on the partial FPGA fabric having a switch matrix.

18 Digital Design Physical Implementation Figure 7.17 Implementing the extended seatbelt warning light circuit on the partial FPGA fabric having a switch matrix. Italicized bits are unused.

19 Digital Design Physical Implementation Figure 7.18 An FPGA with configurable logic blocks, which contain flip-flops along with a lookup table.We’ve put 0s in all the configuration memory bit cells in the figure.

20 Digital Design Physical Implementation Figure 7.19 Implementing a sequential circuit on an FPGA.

21 Digital Design Physical Implementation Figure 7.20 FPGA architecture.

22 Digital Design Physical Implementation Figure 7.21 Programming an FPGA: all configuration bit cells exist in a scan chain (top); a scan chain conceptually is a big shift register (middle); a bit file’s contents would be shifted in during programming -- some relationships between the file’s bits and configuration bit cells are shown (bottom).

23 Digital Design Physical Implementation Figure 7.22 Example logic IC.

24 Digital Design Physical Implementation Figure series IC.

25 Digital Design Physical Implementation Table 7.1 Commonly-used 7400-series ICs

26 Digital Design Physical Implementation Figure 7.24 Implementing the seat-belt warning circuit with 74LS series ICs.

27 Digital Design Physical Implementation Figure 7.25 Implementing the seat-belt warning circuit with one 74LS IC, namely the 74LS27 consisting of three 3-input NOR gates.

28 Digital Design Physical Implementation Figure 7.26 A basic example of a programmable logic device. (AND gates are wired-AND).

29 Digital Design Physical Implementation Figure 7.27 Two types of programmable nodes: (top) fuse based, (bottom) memory based.

30 Digital Design Physical Implementation Figure 7.28 Simplified PLD drawing.

31 Digital Design Physical Implementation Figure 7.29 Seat-belt warning system on a simple PLD.

32 Digital Design Physical Implementation Figure 7.30 (a) PLD with two outputs, (b) PLD with programmable registered outputs.

33 Digital Design Physical Implementation Table 7.2 Sample % of new implementations in various technologies. Total is more than 100% due to overlap among categories. Source: Synopsys, DAC 2002 panel.