2. FIGURE Memory map for the 8088 interface in Figure 7-22 and decoder in Figure The 64K SRAM is mapped to the address range E0000H to EFFFFH.
John Uffenbeck The 80x86 Family: Design, Programming, and Interfacing, 3e
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3. FIGURE 7-25 Decoder to map the SRAM in Figure 7-22 to the range C0000-CFFFFH.
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4. FIGURE (a) NAND, (b) AND, (c) OR, and (d) NOR gates can be used as address decoders, depending on the logic levels to be detected and the output level required.
John Uffenbeck The 80x86 Family: Design, Programming, and Interfacing, 3e
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5. FIGURE 7-33 Two equivalent 8086 address decoder circuits
FIGURE Two equivalent 8086 address decoder circuits. (a) NAND gate implementation. (b) OR gate implementation.
John Uffenbeck The 80x86 Family: Design, Programming, and Interfacing, 3e
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8. FIGURE 7-34 128 MB memory array consisting of eight 16 MB SIMMs
FIGURE MB memory array consisting of eight 16 MB SIMMs. A 74LS138 is used as a block decoder.
John Uffenbeck The 80x86 Family: Design, Programming, and Interfacing, 3e
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9. FIGURE 7-35 Address and byte enable line usage for the 128 MB memory interface in Figure 7-34.
John Uffenbeck The 80x86 Family: Design, Programming, and Interfacing, 3e
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10. FIGURE 7-36 Memory map for the 128 MB memory interface in Figure 7-34
FIGURE Memory map for the 128 MB memory interface in Figure The circuit is mapped to the bottom 128 MB.
John Uffenbeck The 80x86 Family: Design, Programming, and Interfacing, 3e
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11. Decoder

13. Decoder

14. 677 address comparator

15. FIGURE 7-39 Partial diagram of a PAL
FIGURE Partial diagram of a PAL. The AND gate connections are fuse programmable, but the inputs to the OR gate are fixed. (From J. Uffenbeck, Digital Electronics, A Modern Approach, Prentice Hall, Englewood Cliffs, NJ, 1994.)
John Uffenbeck The 80x86 Family: Design, Programming, and Interfacing, 3e
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16. FIGURE Equivalent symbology for a three-input AND gate: (a) standard notation; (b) PAL notation.
John Uffenbeck The 80x86 Family: Design, Programming, and Interfacing, 3e
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17. FIGURE Two equivalent logic diagrams for the function OUT = , (a) standard symbology; (b) PAL notation.
John Uffenbeck The 80x86 Family: Design, Programming, and Interfacing, 3e
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18. FIGURE 7-42 Logic diagram for the 16-input 8-output PAL16L8
FIGURE Logic diagram for the 16-input 8-output PAL16L8. (Copyright Advanced Microdevices, Inc. Reprinted with permission of the copyright owner. All rights reserved.)
John Uffenbeck The 80x86 Family: Design, Programming, and Interfacing, 3e
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19. PLA & GLA

20. EPROM as an address decoder
Add. Data
Data lines will be used as memory chips select lines (one data line for each chip)
Unused address lines to be decoded D0 D1 D2 D3
For Example: if the address applied to the EPROM is 000… , only memory chip selected by D2