10/11/05ELEC 5970-001/6970-001 Lecture 121 ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

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Presentation transcript:

10/11/05ELEC / Lecture 121 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Power Analysis: Probability Waveform Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University

10/11/05ELEC / Lecture 122 Digital Signal Waveforms time Transient region Clock period Primary Inputs Gate Outputs

10/11/05ELEC / Lecture 123 Transient Events Path P1 P2 P3

10/11/05ELEC / Lecture 124 Probability Waveform Input vector applied Next input vector applied Vector period Transient interval 0 Steady state Samples of signal, s(t) 0 Prob. waveform, P(t) 1.0 P(t)=0.25 P(t) = Transition probabilities time

10/11/05ELEC / Lecture 125 Probability Simulation

10/11/05ELEC / Lecture 126 Primary Input Pattern Analysis PI bit streamp1p0p01p … … …

10/11/05ELEC / Lecture 127 PI Waveforms T time 0.5 time 0.5 time 0.5 PI 1 PI 2 PI T

10/11/05ELEC / Lecture 128 Probability Simulation 2 time 0.5 time 0.5 PI 2 PI T time T

10/11/05ELEC / Lecture 129 Probability Simulation T 0.5 PI 1 time T T T

10/11/05ELEC / Lecture 1210 Probability Simulation T T T

10/11/05ELEC / Lecture 1211 Power Consumption of a Gate An input change can multiple transitions at the output of a gate. Per vector power consumed by a gate = CV 2 Σ p01(ti) ti ε [0,T]

10/11/05ELEC / Lecture 1212 Methods Related to Probability Waveform Tagged probability simulation (TPS): Four waveforms corresponding to steady states, 00, 01,10 and 11, are explicitly simulated. Dual-transition simulation (Dual-Trans): An improvement of TPS that considers pairs of consecutive transitions and gate delay to filter glitches. Further improvement is possible with supergate analysis to account for signal correlation.

10/11/05ELEC / Lecture 1213 References F. Najm, R. Burch, P. Yang and I. Hajj, “CREST – A Current Estimator for CMOS Circuits,” Proc. IEEE Int. Conf. on CAD, Nov. 1988, pp C.-S. Ding, et al., “Gate-Level Power Estimation using Tagged Probabilistic Simulation,” IEEE Trans. on CAD, vol. 17, no. 11, pp , Nov F. Hu and V. D. Agrawal, “Dual-Transition Glitch Filtering in Probabilistic Waveform Power Estimation,” Proc. IEEE Great Lakes Symp. VLSI, Apr. 2005, pp F. Hu and V. D. Agrawal, “ Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis,” Proc. IEEE Int. Conf. Computer Design, Oct pp

10/11/05ELEC / Lecture 1214 Power Estimation by Prob. Waveform Circuit TPSDualTransSupergate method E avg σE tot E avg σE tot E avg σE tot c c c c c c c c c c c Avg