Introduction to ARM Architecture, Programmer’s Model and Assembler Embedded Systems Programming

ARM Ltd Originally part of a government sponsored IT programme to provide computers in schools –The ‘BBC’ computer, Acorn, then Archimedes. ARM founded in November 1990 –Spun out of Acorn Computers Designs the ARM range of RISC processor cores Licenses ARM core designs to semiconductor partners who fabricate and sell to their customers. –ARM does not fabricate silicon itself Also develop technologies to assist with the design-in of the ARM architecture –Software tools, boards, debug hardware, application software, bus architectures, peripherals etc

Why ARM? Leading provider of 32-bit embedded RISC microprocessors – 75% of market Common architecture High performance Low power consumption Low system cost Solutions for –Embedded real-time systems for mass storage, automotive, industrial and networking applications –Secure applications – smartcards and SIMs Open platforms running complex operating systems

What is RISC? What is RISC –Reduced instructions –fixed length –Use of pipelines to breakdown and speed up processing –Large number of registers – used as very fast onboard RAM –Load-store architecture – must load and store from memory to register via special instructions Overall faster, simpler processer

ARM Architecture Based on the Berkeley RISC machine –Fixed length instructions –Pipe lines –Load/store architecture The ARM is a 32-bit architecture. When used in relation to the ARM: –Byte means 8 bits –Halfword means 16 bits (two bytes) –Word means 32 bits (four bytes) Most ARM’s implement two instruction sets –32-bit ARM Instruction Set –16-bit Thumb Instruction Set Jazelle cores can also execute Java bytecode

ARM and RISC The ARM processors have many features in common with RISC chips – but is not pure RISC –Uses variable cycle instructions –In-line barrel shifter leads to complex instructions –Thumb mode – a 16 bit extension to ARM assembler –Conditional execution of instructions –Enhanced instructions – ie DSP instructions ARM processors are well adapted to embedded, low power and mobile solutions

Architecture Variants ARMv1 –First version of ARM processor – 26-bit addressing, no multiply / coprocessor ARMv2 – ARM2, First commercial chip –Included 32-bit result multiply instructions / coprocessor support ARMv2a –ARM3 chip with on-chip cache – Added atomic load and store – Coprocessor 15 (cache management) ARMv3 – ARM6, first processor after being independent – 32-bit addressing, separate CPSR, SPSR, virtual memory support

Architecture Variants ARMv4 –added half- word load and store. ARMv5 – improved ARM and Thumb interworking, count leading- zeroes (CLZ) instruction, and architecture variants: – E – enhanced DSP instructions including saturated arithmetic operations and 16- bit multiply operations –J – support for new Java state, offering hardware and optimized software acceleration of bytecode execution. ARMv6 –Include ‘TEJ’ enhancements Memory management, multiprocessing, SIMD instructions –6 new status bits (GE[3:0], E-, A- bits)

Memory Formats The ARM views memory as a linear collection of bytes numbered upwards from zero. Bytes 0 to 3 hold the first stored word, bytes 4 to 7 the second and so on. The ARM can treat words in memory as being stored either in Big Endian or Little Endian format. A word is 32 bits Addresses are 32 bits

Little endian addresses of bytes within words In little endian format, the lowest numbered byte in a word is considered the word’s least significant byte, and the highest numbered byte the most significant. Byte 0 of the memory system is therefore connected to data lines 7 through 0.

Big endian addresses of bytes within words In big endian format, the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. Byte 0 of the memory system is therefore connected to data lines 31 through 24.

ARM processor modes

The ARM register set

Program Status Register format In user programs only the top 4 bits of the CPSR are relevant N - the result was negative Z - the result was zero C - the result produced a carry out V - the result generated an arithmetic overflow I, F – interrupt enable bits T – instruction set (Thumb/ARM)

The CPSR mode bits

Exception processing modes

ARM 7 internals

The ARM instruction set a) Data processing instructions b) Data transfer instructions c) Control flow & conditional execution d) Special instructions

Data processing instructions ALL operands are 32-bits wide and either: come from registers, or are literals (´immediate´ values ) specified in the instruction The result, if any, is 32-bits wide and goes into a register –except long multiplies generate 64-bit results All operand and result registers are specified independently