1. Agenda Programmers Model Instruction Sets System Design
Introduction to ARM Ltd
Programmers Model
Instruction Sets
System Design
Development Tools
Programmers Model
The structure of the ARM architecture
How it has developed
Register set, modes and exceptions
The endian issue

7. ARM7TDMI

9. code density is less so an application in RISC is likely to consume more memory than the equivalent in CISC; however the ARM has a few tricks up its sleeve to reverse this assumption. The ARM lends itself to clean, concise code which is simpler to work with and understand
As typical RAM sizes increased, and after the development of the separate instruction cache large enough to contain inner loops and common subroutines (so code density had much less effect on CPU performance metrics)
byte efficiency", "code efficiency", "operation length reduction", etc. to refer to more-or-less the same concept as code density

12. ARM Partnership Model
ARM’s business model centres around the principle of partnership. At the centre of this are ARM’s semiconductor partners who design, manufacture and market ARM-compliant products.
Having so many partner companies producing silicon executing the same instruction set is a very important part of ARM’s strength in the market place.
However each of our semiconductor partners bring their own unique strengths to the partnership - each having their own technologies, applications knowledge, product focus, culture, geography, and key customers.
In addition to our partnering with semiconductor companies, we also partner with a large number of other third parties to ensure that operating systems, EDA and software development tools, application software and design services are available for doing ARM based designs.
“ATAP” stands for ARM Technology Access Program. Creates a network of independent design service companies and equips them to deliver ARM-powered designs. Members get access to ARM technology, expertise and support. Members sometimes referred to as “Approved Design Centers”.

13. ARM Powered Products

14. Programmers Model
The structure of the ARM architecture
How it has developed
Register set, modes and exceptions
The endian issue

15. The ARM Architecture

16. Data Sizes and Instruction Sets
The ARM is a 32-bit architecture.
When used in relation to the ARM:
Byte means 8 bits
Halfword means 16 bits (two bytes)
Word means 32 bits (four bytes)
Most ARM’s implement two instruction sets
32-bit ARM Instruction Set
16-bit Thumb Instruction Set
Jazelle cores can also execute Java bytecode
The cause of confusion here is the term “word” which will mean 16-bits to people with a 16-bit background.
In the ARM world 16-bits is a “halfword” as the architecture is a 32-bit one, whereas “word” means 32-bits.
Java bytecodes are 8-bit instructions designed to be architecture independent. Jazelle transparently executes most bytecodes in hardware and some in highly optimized ARM code. This is due to a tradeoff between hardware complexity (power consumption & silicon area) and speed.

17. Processor Modes
The Programmers Model can be split into two elements - first of all, the processor modes and secondly, the processor registers. So let’s start by looking at the modes.
Now the typical application will run in an unprivileged mode know as “User” mode, whereas the various exception types will be dealt with in one of the privileged modes : Fast Interrupt, Supervisor, Abort, Normal Interrupt and Undefined (and we will look at what causes each of the exceptions later on).
NB - spell out the word FIQ, otherwise you are saying something rude in German!
One question here is what is the difference between the privileged and unprivileged modes? Well in reality very little really - the ARM core has an output signal (nTRANS on ARM7TDMI, InTRANS, DnTRANS on 9, or encoded as part of HPROT or BPROT in AMBA) which indicates whether the current mode is privileged or unprivileged, and this can be used, for instance, by a memory controller to only allow IO access in a privileged mode. In addition some operations are only permitted in a privileged mode, such as directly changing the mode and enabling of interrupts.
All current ARM cores implement system mode (added in architecture v4). This is simply a privileged version of user mode. Important for re-entrant exceptions because no exceptions can cause system mode to be entered.

19. The ARM Register Set Current Visible Registers Banked out Registers
Abort Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9
r10
r11
r12
r15 (pc)
cpsr
r13 (sp)
r14 (lr)
spsr
Current Visible Registers
Banked out Registers
User
FIQ
IRQ
SVC
Undef r0 r1 r2 r3 r4 r5 r6 r7
r15 (pc)
cpsr
r13 (sp)
r14 (lr)
spsr r8 r9
r10
r11
r12
Current Visible Registers
Banked out Registers
User
IRQ
SVC
Undef
Abort
FIQ Mode
SVC Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9
r10
r11
r12
r15 (pc)
cpsr
r13 (sp)
r14 (lr)
spsr
Current Visible Registers
Banked out Registers
User
FIQ
IRQ
Undef
Abort
Undef Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9
r10
r11
r12
r15 (pc)
cpsr
r13 (sp)
r14 (lr)
spsr
Current Visible Registers
Banked out Registers
User
FIQ
IRQ
SVC
Abort r0 r1 r2 r3 r4 r5 r6 r7 r8 r9
r10
r11
r12
r13 (sp)
r14 (lr)
r15 (pc)
cpsr
spsr
FIQ
IRQ
SVC
Undef
Abort
User Mode
Current Visible Registers
Banked out Registers
IRQ Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9
r10
r11
r12
r15 (pc)
cpsr
r13 (sp)
r14 (lr)
spsr
Current Visible Registers
Banked out Registers
User
FIQ
SVC
Undef
Abort
This animated slide shows the way that the banking of registers works. On the left the currently visible set of registers are shown for a particular mode.
On the right are the registers that are banked out whilst in that mode.
There is a different register bank for each processor mode. The banked registers give rapid context switching for dealing with processor exceptions and privileged operations.
Each key press will switch mode:
user -> FIQ ->user -> IRQ -> user ->SVC -> User -> Undef -> User -> Abort and then back to user.
The following slide then shows this in a more static way that is more useful for reference
Link register – for storing return address
Sp for storing local variables etc

20. Register Organization Summary
User
FIQ
IRQ
SVC
Undef
Abort r8 r9
r10
r11
r12
r13 (sp)
r14 (lr)
r15 (pc)
cpsr r0 r1 r2 r3 r4 r5 r6 r7
User mode r0-r7, r15, and cpsr
User mode r0-r12, r15, and cpsr
User mode r0-r12, r15, and cpsr
User mode r0-r12, r15, and cpsr
User mode r0-r12, r15, and cpsr
Thumb state
Low registers r8 r9
Thumb state
High registers
r10
r11
r12
r13 (sp)
r13 (sp)
r13 (sp)
r13 (sp)
r13 (sp)
r14 (lr)
r14 (lr)
r14 (lr)
r14 (lr)
r14 (lr)
This slide shows the registers visible in each mode - basically in a more static fashion than the previous animated slide that is more useful for reference.
The main point to state here is the splitting of the registers in Thumb state into Low and High registers.
ARM register banking is the minimum necessary for fast handling of overlapping exceptions of different types (e.g. ABORT during SWI during IRQ). For nested exceptions of the same type (e.g. re-entrant interrupts) some additional pushing of registers to the stack is required.
a computer program or subroutine is called reentrant if it can be interrupted in the middle of its execution and then safely be called again ("re-entered") before its previous invocations complete execution
spsr
spsr
spsr
spsr
spsr
Note: System mode uses the User mode register set

21. Program Status Registers

23. Program Status Registers
Interrupt Disable bits.
I = 1: Disables the IRQ.
F = 1: Disables the FIQ.
T Bit
Architecture xT only
T = 0: Processor in ARM state
T = 1: Processor in Thumb state
GE for SIMD instructions
Mode bits
Specify the processor mode
Condition code flags
N = Negative result from ALU
Z = Zero result from ALU
C = ALU operation Carried out
V = ALU operation oVerflowed
Sticky Overflow flag - Q flag
Architecture 5TE/J only
Indicates if saturation has occurred
J bit
Architecture 5TEJ only
J = 1: Processor in Jazelle state
Green psr bits are only in certain versions of the ARM architecture
ALU status flags (set if "S" bit set, implied in Thumb state).
Sticky overflow flag (Q flag) is set either when
saturation occurs during QADD, QDADD, QSUB or QDSUB, or
the result of SMLAxy or SMLAWx overflows 32-bits
Once flag has been set can not be modified by one of the above instructions and must write to CPSR using MSR instruction to cleared
PSRs split into four 8-bit fields that can be individually written:
Control (c) bits 0-7
Extension (x) bits 8-15 Reserved for future use
Status (s) bits Reserved for future use
Flags (f) bits 24-31
Bits that are reserved for future use should not be modified by current software. Typically, a read-modify-write strategy should be used to update the value of a status register to ensure future compatibility. Note that the T/J bits in the CPSR should never be changed directly by writing to the PSR (use the BX/BXJ instruction to change state instead).
However, in cases where the processor state is known in advance (e.g. on reset, following an interrupt, or some other exception), an immediate value may be written directly into the status registers, to change only specific bits (e.g. to change mode).
New ARM V6 bits now shown.

24. Program Counter (r15) When the processor is executing in ARM state:
All instructions are 32 bits wide
All instructions must be word aligned
Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as instruction cannot be halfword or byte aligned).
When the processor is executing in Thumb state:
All instructions are 16 bits wide
All instructions must be halfword aligned
Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as instruction cannot be byte aligned).
When the processor is executing in Jazelle state:
All instructions are 8 bits wide
Processor performs a word access to read 4 instructions at once
ARM is designed to efficiently access memory using a single memory access cycle. So word accesses must be on a word address boundary, halfword accesses must be on a halfword address boundary. This includes instruction fetches.
Point out that strictly, the bottom bits of the PC simply do not exist within the ARM core - hence they are ‘undefined’. Memory system must ignore these for instruction fetches.
In Jazelle state, the processor doesn’t perform 8-bit fetches from memory. Instead it does aligned 32-bit fetches (4-byte prefetching) which is more efficient. Note we don’t mention the PC in Jazelle state because the ‘Jazelle PC’ is actually stored in r14 - this is technical detail that is not relevant as it is completely hidden by the Jazelle support code.

25. ‘s memory organization
Byte addressed memory
Maximum 232 bytes of memory
A word = 32-bits, half-word = 16 bits
Words aligned on 4-byte boundaries
NB - Lowest byte address = LSB of word
“Little-endian”
Word addresses follow LSB byte address 20 16 12 8 4