ECE C03 Lecture 61 Lecture 6 Arithmetic Logic Circuits Hai Zhou ECE 303 Advanced Digital Design Spring 2002

ECE C03 Lecture 62 Outline Review of Number Systems Adders –Ripple carry –Carry Lookahead –Carry Select Combinational Multipliers Arithmetic and Logic Unit (ALU) General Logic Function Units READING: Katz 5.2.1, 5.2.2, 5.2.4, 5.3, 5.5, 4.6

ECE C03 Lecture 63 Review of Number Systems Representation of positive numbers same in most systems Differences in negative numbers Three major schemes: –sign and magnitude –ones complement –twos complement Assumptions: –we'll assume a 4 bit machine word –16 different values can be represented –roughly half are positive, half are negative

ECE C03 Lecture 64 High order bit is sign: 0 = positive (or zero), 1 = negative Three low order bits is the magnitude: 0 (000) thru 7 (111) Number range for n bits = +/-2 -1 Representations for 0 Cumbersome addition/subtraction Must compare magnitudes to determine sign of result n-1 Sign Magnitude Number System

ECE C03 Lecture 65 Twos Complement Representation Only one representation for 0 One more negative number than positive number like 1's comp except shifted one position clockwise

ECE C03 Lecture 66 Twos Complement Number System N* = 2 - N n Example: Twos complement of 7 2 = = = repr. of -7 Example: Twos complement of = = = repr. of 7 4 sub Shortcut method: Twos complement = bitwise complement > > 1001 (representation of -7) > > 0111 (representation of 7)

ECE C03 Lecture 67 Addition and Subtraction of Numbers Sign and Magnitude (-3) result sign bit is the same as the operands' sign when signs differ, operation is subtract, sign of result depends on sign of number with the larger magnitude

ECE C03 Lecture 68 Twos Complement Addition and Subtraction Twos Complement Calculations (-3) If carry-in to sign = carry-out then ignore carry if carry-in differs from carry-out then overflow Simpler addition scheme makes twos complement the most common choice for integer number systems within digital systems

ECE C03 Lecture 69 Twos Complement Addition and Subtraction Why can the carry-out be ignored? -M + N when N > M: M* + N = (2 - M) + N = 2 + (N - M) n n Ignoring carry-out is just like subtracting 2 n -M + -N where N + M < or = 2 n-1 -M + (-N) = M* + N* = (2 - M) + (2 - N) = 2 - (M + N) + 2 n n After ignoring the carry, this is just the right twos compl. representation for -(M + N)! nn

ECE C03 Lecture 610 Circuits for Binary Addition Half Adder With twos complement numbers, addition is sufficient Half-adder Schematic

ECE C03 Lecture 611 Full Adder Cascaded Multi-bit Adder usually interested in adding more than two bits this motivates the need for the full adder

ECE C03 Lecture 612 Full Adder S = CI xor A xor B CO = B CI + A CI + A B = CI (A + B) + A B

ECE C03 Lecture 613 Full Adder Circuit A A A B B B CI S CO Alternative Implementation: 5 Gates Half Adder A B Half Adder A + B CI A + B + CI SS CO CI (A + B) A B S CO A B + CI (A xor B) = A B + B CI + A CI Standard Approach: 6 Gates +

ECE C03 Lecture 614 Adder/Subtractor A - B = A + (-B) = A + B + 1 AB CO S +CI AB CO S +CI AB CO S +CI AB CO S +CI 01 Add/Subtract A 3 B 3 B 3 01 A 2 B 2 B 2 01 A 1 B 1 B 1 01 A 0 B 0 B 0 Sel S 3 S 2 S 1 S 0 Overflow

ECE C03 Lecture 615 Delay Analysis of Ripple Adder Carry out of a single stage can be implemented in 2 gate delays For a 16 bit adder, the 16th bit carry is generated after 16 * 2 = 32 gate delays. The sum bit takes one additional gate delay to generate the sum of the 16th bit after 15th bit carry –15 * = 31 gate delays Takes too long - need to investigate FASTER adders!

ECE C03 Lecture 616 Carry Lookahead Adder Critical delay: the propagation of carry from low to high order stages A A B B @N+2 late arriving signal two gate delays to compute CO 4 stage adder final sum and carry A 0 B 0 C 0 S A 1 B 1 C 1 S A 2 B 2 C S A 3 B 3 C S C

ECE C03 Lecture 617 Carry Lookahead Circuit Critical delay: the propagation of carry from low to high order stages worst case addition T0: Inputs to the adder are valid T2: Stage 0 carry out (C1) T4: Stage 1 carry out (C2) T6: Stage 2 carry out (C3) T8: Stage 3 carry out (C4) 2 delays to compute sum but last carry not ready until 6 delays later T0T2T4T6T8 S0, C1 ValidS1, C2 ValidS2, C3 ValidS3, C4 Valid

ECE C03 Lecture 618 Carry Lookahead Logic Carry Generate Gi = Ai Bi must generate carry when A = B = 1 Carry Propagate Pi = Ai xor Bi carry in will equal carry out here Si = Ai xor Bi xor Ci = Pi xor Ci Ci+1 = Ai Bi + Ai Ci + Bi Ci = Ai Bi + Ci (Ai + Bi) = Ai Bi + Ci (Ai xor Bi) = Gi + Ci Pi Sum and Carry can be reexpressed in terms of generate/propagate:

ECE C03 Lecture 619 Carry Lookahead Logic Reexpress the carry logic as follows: C1 = G0 + P0 C0 C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 C0 C3 = G2 + P2 C2 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0 C4 = G3 + P3 C3 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0 Each of the carry equations can be implemented in a two-level logic network Variables are the adder inputs and carry in to stage 0!

ECE C03 Lecture 620 Carry Lookahead Implementation Adder with Propagate and Generate Outputs Increasingly complex logic 1 gate delay Ci 2 gate delays Bi Ai 1 gate delay P3 G3 C4

ECE C03 Lecture 621 Cascaded Carry Lookahead Logic Carry lookahead logic generates individual carries sums computed much faster A 0 B 0 C 0 S A 1 B 1 C S A 2 B 2 C S A 3 B 3 C S C

ECE C03 Lecture 622 Delay Analysis in Carry Lookahead Assume a 4-stage adder with CLA Propagate and generate signals available after 1 gate delays Carry signals for slices 1 to 4 available after 3 gate delays Sum signal for slices 1 to 4 after 4 gate delays

ECE C03 Lecture 623 Carry Lookahead Logic Cascaded Carry Lookahead 4 bit adders with internal carry lookahead second level carry lookahead unit, extends lookahead to 16 bits 4-bitAdder 44 4 A[15-12]B C 12 C 16 S[15-12] P G 4-bitAdder 44 4 A[11-8]B[11-8] C 8 S[11-8] P G 4-bitAdder 44 4 A[7-4]B C 4 S P G 4-bitAdder A[3-0]B C 0 S PG Lookahead Carry Unit C 0 P 0 G 0 P 1 G 1 P 2 G 2 P 3 G 3 C 3 C 2 C 1 C 0 P3-0G @5 C 16

ECE C03 Lecture 624 Delay Analysis of Carry Lookahead Consider a 16-bit adder Implemented with four stages of 4-bit adders using carry lookahead Carry in to the highest stage is available after 5 gate delays Sum from highest stage available at 8 gate delays COMPARE WITH 32 gate delays for a ripple carry adder NOTE HOWEVER THIS ASSUMES ALL GATE DELAYS ARE SAME Not true, delays depand on fan-ins and fan-out

ECE C03 Lecture 625 Theory of Multiplication Basic Concept multiplicand multiplier 1101 (13) 1011 (11) * (143) Partial products product of 2 4-bit numbers is an 8-bit number

ECE C03 Lecture 626 Combinational Multiplier Partial Product Accumulation A0 B0 A0 B0 A1 B1 A1 B0 A0 B1 A2 B2 A2 B0 A1 B1 A0 B2 A3 B3 A2 B0 A2 B1 A1 B2 A0 B3 A3 B1 A2 B2 A1 B3 A3 B2 A2 B3 A3 B3 S6 S5 S4 S3S2 S1S0 S7

ECE C03 Lecture 627 Partial Product Accumulation Note use of parallel carry-outs to form higher order sums 12 Adders, if full adders, this is 6 gates each = 72 gates 16 gates form the partial products total = 88 gates!

ECE C03 Lecture 628 Combinational Multiplier Another Representation of the Circuit Building block: full adder + and 4 x 4 array of building blocks

ECE C03 Lecture 629 Arithmetic Logic Unit Design Sample ALU Logical and Arithmetic Operations Not all operations appear useful, but "fall out" of internal logic

ECE C03 Lecture 630 Arithmetic Logic Unit Design Sample ALU Traditional Design Approach Truth Table & Espresso 23 product terms! Equivalent to 25 gates.i 6.o 2.ilb m s1 s0 ci ai bi.ob fi co.p e Fi Ci+1 X X X X X X X X X X X X X X X X

ECE C03 Lecture 631 Arithmetic Logic Unit Design Sample ALU Multilevel Implementation.model alu.espresso.inputs m s1 s0 ci ai bi.outputs fi co.names m ci co [30] [33] [35] fi names m ci [30] [33] co names s0 ai [30] names m s1 bi [33] names s1 bi [35] end 12 Gates \S1 \Bi [35] M M M S1 Bi [33] S0 Ai [30] Ci Co \Co \[30] \[35] Fi