OK, we are now ready to begin Chapter 2 of our text We will begin looking at some preliminary stuff Then we will look at the the Intel IA-32 (CISC) Then we will concentrate on the MIPS 32 (RISC) Note: A number of the slides I will use for Patterson & Hennessy material are adapted, with permission, from slides of a computer engineering colleague: Professor Mary Jane Irwin of Penn State

Where is the Market? Millions of Computers For “definitions” of desktop, servers, supercomputers (100’s to 1000’s of processors, Gbytes to Tbytes of main memory, Tbytes to Pbytes of secondary storage), and embedded systems (cell phones, automobile control, video games, entertainment systems (digital TVs), PDAs, etc.). The computer (IT) industry is responsible for almost 10% of the GNP of the US. The embedded market has shown the strongest growth (40% compounded annual growth compared to only 9% for desktops – where do laptops fit?). This chart/number does not include the low-end 8-bit and 16-bit embedded processors that are everywhere! This is a good slide to talk about the other performance metrics in addition to speed (or see if the students can come up with them) including Power, space/volume, memory space, cost, reliability

ISA Type Sales Millions of Processor Only includes 32- and 64-bit processors Others includes Samsung, HP, AMD, TI, Transmeta (same ISA as IA-32), …

Moore’s Law In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 24 months (i.e., grow exponentially with time). The million transistor/chip barrier was crossed in the 1980’s. 2300 transistors, 1 MHz clock (Intel 4004) - 1971 16 Million transistors (Ultra Sparc III) 42 Million transistors, 2 GHz clock (Intel Xeon) – 2001 55 Million transistors, 3 GHz, 130nm technology, 250mm2 die (Intel Pentium 4) - 2004 140 Million transistor (HP PA-8500) Tbyte = 2^40 bytes (or 10^12 bytes) Note that Moore’s law is not about speed predictions but about chip complexity

Processor Performance Increase Intel Pentium 4/3000 DEC Alpha 21264A/667 DEC Alpha 21264/600 Intel Xeon/2000 DEC Alpha 5/500 DEC Alpha 4/266 DEC Alpha 5/300 DEC AXP/500 IBM POWER 100 HP 9000/750 IBM RS6000 Another powerpoint “comic” – note that the y axis is log ! x/y where x is the model number and y is the speed in MHz Rate of performance improvement has been between 1.5 and 1.6 times per year – how much longer will Moore’s Law hold? MIPS M2000 SUN-4/260 MIPS M/120

DRAM Capacity Growth 512M 256M 128M 64M 16M 4M 1M 256K 64K 16K Memories have quadrupled capacity every 3 years (up until 1996) – a 60% increse per year for 20 years. Now is doubling in capacity every two years. 16K

Computer Instruction Formats Three operand e.g. Opcode Source1, Source2, Destination Two operand e.g. Opcode Source1, Source2Destination One operand is used as Source & Destination One operand e.g. Opcode Source Result is deposited in an Accumulator

The Intel IA 32

History of the IA-32 (Intel) 1971 – 4004 built by Intel as a calculator engine 1972 – 8008 introduced as an 8 bit computer 1974 – 8080 an 8 bit (16 address bit) enough power to build a computer around it – Altair 8800, IMSAI 8080, Osborne I (first portable computer 1981) 1976 – 8085 8080 with two interrupts 1978 – 8086 16 bit machine using enhanced 8080 instr & Reg 1980 - 8087 8086 floating pt co-processor 1981 - 8088 8 bit external data bus 1982 – 80186 & 80286 the later was the engine for the first IBM PC, added memory management to become a multiuser machine 1985 – 80386 32 bit machine with 32 bit address space 1989 – 80486 multiprogramming, pseudo GPR machine 1992 – Pentium & Pentium Pro (1995) higher performance 1997 - Added MMX media extentions 1999 – Added another 70 instructions 2001 – Added another 144 instructions 2003 - Amdahl architecture increased address space to 64 bits and breaks legacy chain 2004 – Intel adopts AMD64 architecture with slight addition Building a legacy nightmare !

IA-32 Registers

IA-32 Registers

IA-32 Flags Register

Example IA-32 Instruction Format

Sample IA-32 Instruction Formats Note: Instruction lengths vary from 1 to 17 bytes

The MIPS 32

RISC - Reduced Instruction Set Computer RISC philosophy (keep it simple!) fixed instruction length(s) (one word?) load-store instruction sets (don’t do anything else) limited addressing modes limited operations MIPS, Sun SPARC, HP PA-RISC, IBM PowerPC, Intel (Compaq), Alpha, … Instruction sets are measured by how well compilers use them as opposed to how well assembly language programmers use them As opposed to CISC – Complicated Instruction Set Architecture (ala the x86) Design goals: speed, cost (design, fabrication, test, packaging), size, power consumption, reliability, memory space (embedded systems)

MIPS R3000 Instruction Set Architecture (ISA) Registers Instruction Categories Computational Load/Store Jump and Branch Floating Point coprocessor Memory Management Special R0 - R31 PC HI LO OP rs rt rd sa funct immediate jump target 3 Instruction Formats: all 32 bits wide R format I format J format

MIPS Addressing Modes 1. Operand: Register addressing Register op rs rt rd funct Register word operand op rs rt offset 2. Operand: Base addressing base register Memory word or byte operand 3. Operand: Immediate addressing op rs rt operand 4. Instruction: PC-relative addressing op rs rt offset Memory branch destination instruction Program Counter (PC) 5. Instruction: Pseudo-direct addressing Memory op jump address || jump destination instruction Program Counter (PC)

MIPS Register Convention Name Register Number Usage Preserve on call? $zero constant 0 (hardware) n.a. $at 1 reserved for assembler $v0 - $v1 2-3 returned values no $a0 - $a3 4-7 arguments yes $t0 - $t7 8-15 temporaries $s0 - $s7 16-23 saved values $t8 - $t9 24-25 $gp 28 global pointer $sp 29 stack pointer $fp 30 frame pointer $ra 31 return addr (hardware)

MIPS 32 “Card”

MIPS Register File Holds thirty-two 32-bit registers Registers are Two read ports and One write port 32 bits 5 32 src1 addr src1 data 5 src2 addr 32 locations 5 dst addr Registers are Faster than main memory But register files with more locations are slower (e.g., a 64 word file could be as much as 50% slower than a 32 word file) Read/write port increase impacts speed quadratically Easier for a compiler to use e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order vs. stack Can hold variables so that code density improves (since register are named with fewer bits than a memory location) 32 src2 data 32 write data write control All machines (since 1975) have used general purpose registers How many bits wide are each of the lines going into/out of the register file?

MIPS Organization Processor Memory 1…1100 read/write addr 230 words Register File 1…1100 src1 addr src1 data 5 32 src2 addr 32 registers ($zero - $ra) 5 dst addr read/write addr 5 src2 data write data 32 230 words 32 32 32 bits branch offset read data 32 Add PC 32 32 32 32 Add 32 4 write data 0…1100 Fetch PC = PC+4 Decode Exec 32 0…1000 32 4 5 6 7 0…0100 32 ALU 1 2 3 0…0000 32 word address (binary) 32 bits 32 byte address (big Endian)