1. Lecture 8. MIPS Instructions #1 – Arithmetic and Logical Instructions Prof. Taeweon Suh Computer Science Education Korea University 2010 R&E Computer System Education & Research

2. Korea Univ MIPS Stanford University led by John Hennessy started work on MIPS in 1981  John is currently a president of Stanford Univ. MIPS has 32-bit and 64-bit versions  We focus on 32-bit version Currently, MIPS is primarily used in many embedded systems  Nintendo 64  Sony Playstation and Playstation 2  Cisco routers 2

3. Korea Univ CISC vs RISC CISC (Complex Instruction Set Computer)  One assembly instruction does many (complex) job  Variable length instruction  Example: x86 (Intel, AMD) RISC (Reduced Instruction Set Computer)  Each assembly instruction does a small (unit) job  Fixed-length instruction  Load/Store Architecture  Example: MIPS, ARM 3

4. Korea Univ Let’s go over MIPS instructions  Again, if you completely understand one CPU, it is pretty easy to understand other CPUs For the term project, you should implement the MIPS ISA into hardware 4

5. Korea Univ Overview of a MIPS Operation (Computer Hardware) Every computer must be able to perform arithmetic MIPS arithmetic in assembly form addR3, R1, R5 # R3 = R1 + R5 An instruction operates on operands ( R3, R1, and R5 are all operands) # indicate a comment, so assembler ignores it  Operands of arithmetic instructions come from special locations called registers or from the immediate field in instructions All CPUs (x86, PowerPC, MIPS…) have registers inside  Registers are visible to the programmers Again, abstraction layer! When CPU completes a arithmetic operation (such as addition), its result is stored in a register  MIPS has a register file consisting of 32 32-bit registers 5

6. Korea Univ CPU (MIPS) Simple Illustration of the CPU Internal Organization 6 R0 R1 R2 R3 R30 R31 … 32 bits Registers R1 R5 R3 + addR3, R1, R5 # R3 = R1 + R5 What kinds of other instructions do you think CPU should have? Memory Address Bus Data Bus add R3, R1, R5

7. Korea Univ MIPS Register File MIPS register file has thirty-two 32- bit registers  Two read ports  One write port Registers are implemented with flip-flops  For example, one 32-bit register requires 32 flop-flops Registers are much faster than main memory since they reside inside CPU So, compilers strive to use registers when translating high-level code to assembly code 7 Register File dst addr src1 addr src2 addr 32 bits src1 data 32 5 src2 data 32 write data 32 write control 5 R0 R1 R2 R3 R30 R31 … 5

8. Korea Univ Register File in Verilog 8 module regfile(input clk, input we, input [4:0] ra1, ra2, wa, input [31:0] wd, output [31:0] rd1, rd2); reg [31:0] rf[31:0]; // three ported register file // read two ports combinationally // write third port on rising edge of clock // register 0 hardwired to 0 always @(posedge clk) if (we) rf[wa] <= wd; assign rd1 = (ra1 != 0) ? rf[ra1] : 0; assign rd2 = (ra2 != 0) ? rf[ra2] : 0; endmodule Register File wa3 ra1[4:0] ra2[4:0] 32 bits rd1 32 5 rd2 32 wd3 32 we3 5 R0 R1 R2 R3 R30 R31 … 5

9. Korea Univ MIPS Register Convention 9 NameRegister Number UsagePreserve on call? $zero0constant 0 (hardwired)n.a. $at1reserved for assemblern.a. $v0 - $v12-3returned valuesno $a0 - $a34-7argumentsyes $t0 - $t78-15temporariesno $s0 - $s716-23saved valuesyes $t8 - $t924-25temporariesno $gp28global pointeryes $sp29stack pointeryes $fp30frame pointeryes $ra31return addressyes

10. Korea Univ MIPS-32 CPU Instruction categories  Arithmetic and Logical (Integer)  Load/Store  Jump and Branch  Floating Point 10 R0 - R31 PC HI LO Registers 3 Instruction Formats: all 32 bits wide opcodersrt opcodersrtimmediate opcodejump target rdsafunct R format I format J format

11. Korea Univ MIPS Instruction Fields MIPS fields are given names to make them easier to refer to 11 op6-bitsopcode that specifies the operation rs5-bitsregister of the first source operand rt5-bitsregister of the second source operand rd5-bitsregister of the result’s destination shamt5-bitsshift amount (for shift instructions) funct6-bitsfunction code augmenting the opcode op rsrtrdshamtfunct 32-bit

12. Korea Univ MIPS (RISC) Design Principles Simplicity favors regularity  Fixed size instructions  Small number of instruction formats  Opcode always occupies the first 6 bits in instructions Smaller is faster  Limited instruction set  Limited number of registers in register file  Limited number of addressing modes Make the common case fast  Arithmetic operands from the register file (load-store machine)  Allow instructions to contain immediate operands Good design demands good compromises  Three instruction formats 12

13. Korea Univ MIPS Essential Instructions 13

14. Korea Univ MIPS Instructions For the complete instruction set, refer to the “Appendix B.10 MIPS R2000 Assembly Language” For detailed information on the MIPS instruction set, refer to the Appendix A (page 469) in MIPS R4000 specification linked in the class web We are going to cover essential and important instructions in this class 14

15. Korea Univ MIPS Arithmetic Instructions MIPS Arithmetic instructions include add, sub, addi, addiu, mult, div and some more  Check out the appendix for the list of all arithmetic instructions 15 High-level code a = b + c MIPS assembly code # $s0 = a, $s1 = b, $s2 = c add $s0, $s1, $s2 compile

16. Korea Univ MIPS Arithmetic Instruction - add Instruction format (R format) addrd, rs, rt Example: add$t0, $s1, $s2 # $t0 <= $s1 + $s2 16 opcodersrtrdsafunct NameRegister Number $zero0 $at1 $v0 - $v12-3 $a0 - $a34-7 $t0 - $t78-15 $s0 - $s716-23 $t8 - $t924-25 $gp28 $sp29 $fp30 $ra31 017188032 MIPS architect defines the opcode and function 000000binary hexadecimal0x0232 4020 000000 10001 10010 01000 00000 100000 10001 100000 10010 01000 00000

17. Korea Univ MIPS Arithmetic Instruction - sub Instruction format (R format) subrd, rs, rt Example: sub$t2, $s3, $s4 # $t2 <= $s3 - $s4 17 opcodersrtrdsafunct NameRegister Number $zero0 $at1 $v0 - $v12-3 $a0 - $a34-7 $t0 - $t78-15 $s0 - $s716-23 $t8 - $t924-25 $gp28 $sp29 $fp30 $ra31 0192010034 MIPS architect defines the opcode and function 000000binary hexadecimal0x0274 5022 000000 10011 10100 01010 00000 100010 10011 100010 10100 01010 00000

18. Korea Univ Immediate R-type instructions have all 3 operands in registers Operands could be stored in instructions itself in I- type instructions  They are called immediates because they are immediately available from the instructions (I-type) They do not require a register or memory access  16-bit immediate field in MIPS instructions limits values to the range of (-2 15 ~ +2 15 –1) since it uses 2’s complement 18 opcodersrtimmediate I format

19. Korea Univ Revisiting 2’s Complement Number In hardware design of computer arithmetic, the 2s complement number provides a convenient and simple way to do addition and subtraction of unsigned and signed numbers Given an n-bit number N in binary, the 2s complement of N is defined as 2 n – N for N ≠ 0 0 for N = 0  Example: In 4-bit number, 3 is 4’b0011  2’s complement of 3: 2 4 -3 = 4’b1101 A fast way to get a 2s complement number is to flip all the bits and add “1”. 19

20. Korea Univ Number System Comparison with N-bit 20 Number SystemRange Unsigned[0, 2 N -1] Sign/Magnitude[-(2 N-1 -1), 2 N-1 -1] 2’s Complement[-2 N-1, 2 N-1 -1] Thus, 16-bit can represent a range of  Unsigned: [ 0 ~ +(2 16 -1)] = [ 0 ~ +65535]  Sign/Magnitute: [-(2 16-1 -1) ~ +(2 16-1 -1)] =[-32767 ~ +32867]  2’s complement: [-2 16-1 ~ +2 16-1 -1] =[-32768 ~ +32867]

21. Korea Univ MIPS Arithmetic Instruction - addi Instruction format (I format) addirt, rs, imm Example: addi$t0, $s3, -12#$t0 = $s3 + (-12) 21 opcodersrtimmediate 8198-12 NameRegister Number $zero0 $at1 $v0 - $v12-3 $a0 - $a34-7 $t0 - $t78-15 $s0 - $s716-23 $t8 - $t924-25 $gp28 $sp29 $fp30 $ra31 001000binary hexadecimal0x2268 FFF4 001000 10011 01000 11111 11111 110100 10011 110100 01000 11111

22. Korea Univ MIPS Logical Instructions MIPS logical operations include and, andi, or, ori, xor, nor, sll, slr, sra and some more Logical operations operate bit-by-bit on 2 source operands and write the result to the destination register 22 High-level code a = b & c MIPS assembly code # $s0 = a, $s1 = b, $s2 = c and $s0, $s1, $s2 compile

23. Korea Univ AND, OR, and NOR Usages and, or, nor –and : useful for masking bits Example: mask all but the least significant byte of a value: 0xF234012F AND 0x000000FF = 0x0000002F –or: useful for combining bit fields Example: combine 0xF2340000 with 0x000012BC: 0xF2340000 OR 0x000012BC = 0xF23412BC – nor: useful for inverting bits: Example: A NOR $0 = NOT A 23

24. Korea Univ Logical Instruction Examples 24

25. Korea Univ Logical Instruction Examples 25

26. Korea Univ MIPS Logical Instructions Instruction format (R format) and (or, nor) rd, rs, rt Examples: and $t0, $t1, $t2#$t0 = $t1 & $t2 or $t0, $t1, $t2#$t0 = $t1 | $t2 nor $t0, $t1, $t2#$t0 = not($t1 | $t2) 26 opcodersrtrdsafunct NameRegister Number $zero0 $at1 $v0 - $v12-3 $a0 - $a34-7 $t0 - $t78-15 $s0 - $s716-23 $t8 - $t924-25 $gp28 $sp29 $fp30 $ra31 09108039 000000binary hexadecimal0x012A 4027 000000 01001 01010 01000 00000 100111 01001 100111 01010 01000 00000

27. Korea Univ MIPS Logical Instructions (Cont) Instruction format (I format) andi(ori) rt, rs, imm Example: andi $t0, $t1, 0xFF00#$t0 = $t1 & ff00 ori $t0, $t1, 0xFF00#$t0 = $t1 | ff00 27 opcodersrtimmediate 13980xFF00 NameRegister Number $zero0 $at1 $v0 - $v12-3 $a0 - $a34-7 $t0 - $t78-15 $s0 - $s716-23 $t8 - $t924-25 $gp28 $sp29 $fp30 $ra31 001101binary hexadecimal0x3528 FF00 001101 01001 01000 11111 11100 000000 01001 000000 01000 11111 11100

28. Korea Univ Sign Extension & Zero Extension Most MIPS instructions sign-extend the immediate  For example, addi does sign-extension to support both positive and negative immediates An exception to the rule is that logical operations (andi, ori, xori) place 0’s in the upper half  This is called zero extension 28

29. Korea Univ Revisiting Basic Shifting 29 Shift directions  Left (multiply by 2)  Right (divide by 2) Take floor value if the result is not an integer X X,Floor value of X (or  X  ) is the greatest integer number less than or equal to X, E.g.   5/2  = 2   -3/2  = -2 Shift types  Logical (or unsigned)  Arithmetic (or signed)

30. Korea Univ Revisiting Logical Shift 30 Shift Left  MSB: Shifted out  LSB: Shifted in with a “0”  Examples: (11001011 << 1) = 10010110 (11001011 << 3) = 01011000 Shift right  MSB: Shifted in with a “0”  LSB: Shifted out  Examples: (11001011 >> 1) = 01100101 (11001011 >> 3) = 00011001 Logic shifts can be useful to perform multiplication or division of unsigned integer Logical shift right takes floor value if the result is not integer Modified from Prof H.H.Lee’s slide, Georgia Tech

31. Korea Univ Revisiting Arithmetic Shift 31 Shift left  MSB: Shifted out, however, be aware of overflow/underflow  LSB: Shifted in with a “0”  Examples: (1100 <<< 1) = 1000 (1100 <<< 3) = 0000 (Incorrect!)  Underflow Shift right  MSB: Retain “sign bit”  LSB: Shifted out  Examples: (1100 >>> 1) = 1110 (Retain sign bit) (1100 >> >3) = 1111 (  -4/8  = -1 )  Floor value of -0.5 Arithmetic shifts can be useful to perform multiplication or division of signed integer Arithmetic shift right takes floor value if the result is not integer Modified from Prof H.H.Lee’s slide, Georgia Tech

32. Korea Univ MIPS Shift Instructions Shift instructions shift the value in a register left or right by up to 31 bits (5-bit shamt field)  sll rd, rt, shamt: shift left logical  srl rd, rt, shamt: shift right logical  sra rd, rt, shamt: shift right arithmetic (sign-extension) Instruction Format (R format) Examples: sll $t0, $s1, 4 #$t0 = $s1 << 4 bits srl $t2, $s0, 8 #$t2 = $s0 >> 8 bits sra $s3, $s1, 4 #$t0 = $s1 << 4 bits 32 NameRegister Number $zero0 $at1 $v0 - $v12-3 $a0 - $a34-7 $t0 - $t78-15 $s0 - $s716-23 $t8 - $t924-25 $gp28 $sp29 $fp30 $ra31 opcodersrtrdsafunct 00171943 Binary ? Hexadecimal: ?

33. Korea Univ MIPS Shift Instructions (Cont) MIPS also has variable-shift instructions  sllv rd, rt, rs: shift left logical variable  srlv rd, rt, rs: shift right logical variable  srav rd, rt, rs: shift right arithmetic variable Instruction Format (R format) Examples: sllv $s3, $s1, $s2 #$s3 = $s1 << $s2 srlv $s4, $s1, $s2 #$s4 = $s1 >> $s2 srav $s5, $s1, $s2 #$s5 = $s1 << $s2 33 NameRegister Number $zero0 $at1 $v0 - $v12-3 $a0 - $a34-7 $t0 - $t78-15 $s0 - $s716-23 $t8 - $t924-25 $gp28 $sp29 $fp30 $ra31 opcodersrtrdsafunct 018172107 Binary ? Hexadecimal: ?