Design and Implementation of VLSI Systems (EN0160) Lecture 16: Scaling Theory Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson] S. Reda EN160 SP’07

Moore’s Law Moore’s Law. The number of transistors in an integrated circuit doubles every 2 years. IBM Cell 234M transistors in die size of 221 mm2 S. Reda EN160 SP’07

Scaling of MOS transistors 1.2nm minimum feature size (gate length) Current oxide thickness ~ 1.0 – 2.0nm thickness  3 – 4 atomic layers of oxide Power supply voltage scaling S. Reda EN160 SP’07

Scaling Scaling of lithographic wavelength Avg transistor price is 0.1 μcent! Fewer and fewer companies can afford to have their own foundries Number of transistors shipped S. Reda EN160 SP’07

Worldwide semiconductor revenues Box office: worldwide ~$23B US ($9B); tickets + dvds + tv rights: ~ $44B Worldwide total software sales $383B Worldwide pharmaceutical sales: $550B S. Reda EN160 SP’07

Device scaling (very idealistic NMOS transistor) (scaled down by L) scale doping increased by a factor of S Increasing the channel doping density decreases the depletion width  improves isolation between source and drain during OFF status  permits distance between the source and drain regions to be scaled S. Reda EN160 SP’07

Implications of ideal device scaling S. Reda EN160 SP’07

Total power was increasing (mostly because of 2 frequency + die) until we hit a “wall” Intel VP Patrick Gelsinger (ISSCC 2001) “If scaling continues at present pace, by 2005, high speed processors would have power density of nuclear reactor, by 2010, a rocket nozzle, and by 2015, surface of sun.” S. Reda EN160 SP’07

Scaling of standby (leakage) power Standby power bottleneck Even if Vt is kept constant after scaling, Poff scales up by S if tox is scaled down by S Vt must be scaled down if VDD is scaled down (otherwise ISAT is weaker and transistor is slow) Standby power would further increase by 10 for every 0.1V reduction of Vt S. Reda EN160 SP’07

Power/performance tradeoffs increasing performance higher active power leakage Power supply voltage (Vdd) Threshold voltage (Vt) [Taur, 01] S. Reda EN160 SP’07

Interconnect scaling w: width of interconnect (layer dependant) s: spacing between interconnects with same layer h: dielectric thickness (spacing between interconnects in two vertically adjacent layers) l: length of interconnect t: thickness of interconnect S. Reda EN160 SP’07

Constant thickness scaling versus reduced thickness scaling S. Reda EN160 SP’07

Implications of ideal interconnect scaling S. Reda EN160 SP’07

Interconnect delay is dominating gate delay bottleneck Repeaters can help but… S. Reda EN160 SP’07

repeaters required to buffer Itanium global interconnects With scaling the reachable radius of a buffer decreases  we need more and more buffers bottleneck repeaters required to buffer Itanium global interconnects A corner-to-corner (BL-UR) wire in Itanium (180nm) requires 6 repeaters to span die Repeaters consume chip area; consume power; add vias S. Reda EN160 SP’07

Summary We are done with the main (and most of the) material from Chapter 4 (will not discuss reliability) S. Reda EN160 SP’07