Modulo-N Counters Lecture L8.4 Section 7.2. Counters Modulo-5 Counter 3-Bit Down Counter with Load and Timeout Modulo-N Down Counter.

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Presentation transcript:

Modulo-N Counters Lecture L8.4 Section 7.2

Counters Modulo-5 Counter 3-Bit Down Counter with Load and Timeout Modulo-N Down Counter

CLK DQ !Q CLK DQ !Q CLK DQ !Q Q0Q0.D Q1 Q2 Q1.D Q2.D s s s s s s X X X s X X X s X X X State Q2 Q1 Q0 Q2.D Q1.D Q0.D Modulo-5 Counter

s s s s s s X X X s X X X s X X X State Q2 Q1 Q0 Q2.D Q1.D Q0.D Modulo-5 Counter Q2 Q1 Q X 1 Q2.D Q2.D = Q1 & Q0 XX

s s s s s s X X X s X X X s X X X State Q2 Q1 Q0 Q2.D Q1.D Q0.D Modulo-5 Counter Q2 Q1 Q X X 1 Q1.D Q1.D = !Q1 & Q0 # Q1 & !Q0 X

s s s s s s X X X s X X X s X X X State Q2 Q1 Q0 Q2.D Q1.D Q0.D Modulo-5 Counter Q2 Q1 Q X 1 Q0.D Q0.D = !Q2 & ! Q0 XX

mod5cnt.abl MODULE mod5cnt TITLE 'Modulo-5 Counter' DECLARATIONS hex7seg interface([D3..D0] -> [a,b,c,d,e,f,g]); d7R FUNCTIONAL_BLOCK hex7seg; " INPUT PINS " CLK PIN 12; " 1 Hz clock (jumper) clear PIN 11;" switch 1 " OUTPUT PINS " Q2..Q0 PIN 41,43,44 ISTYPE 'reg'; " LED Q = [Q2..Q0]; " 3-bit output vector [a,b,c,d,e,f,g] PIN 15,18,23,21,19,14,17 ISTYPE 'com'; " Rightmost (units) 7-segment LED display

EQUATIONS Q.AR = clear; Q.C = CLK; Q2.D = Q1 & Q0; Q1.D = !Q1 & Q0 # Q1 & !Q0; Q0.D = !Q2 & !Q0; [a,b,c,d,e,f,g] = d7R.[a,b,c,d,e,f,g]; d7R.[D2..D0] = Q; d7R.D3 = 0; mod5cnt.abl (cont’d) Note Asynchronous Clear

mod5cnt.abl (cont’d) test_vectors(CLK -> Q).C. -> 1;.C. -> 2;.C. -> 3;.C. -> 4;.C. -> 0;.C. -> 1;.C. -> 2;.C. -> 3;.C. -> 4;.C. -> 0;.C. -> 1;.C. -> 2; END

Mod5cnt Simulation

Counters Modulo-5 Counter 3-Bit Down Counter with Load and Timeout Modulo-N Down Counter

CLK DQ !Q CLK DQ !Q CLK DQ !Q Q0Q0.D Q1 Q2 Q1.D Q2.D s s s s s s s s State Q2 Q1 Q0 Q2.D Q1.D Q0.D 3-Bit Down Counter

Q2 Q1 Q Q2.D Q2.D = !Q2 & !Q1 & !Q0 # Q2 & Q1 # Q2 & Q0 s s s s s s s s State Q2 Q1 Q0 Q2.D Q1.D Q0.D

3-Bit Down Counter Q2 Q1 Q Q1.D Q1.D = !Q1 & !Q0 # Q1 & Q0 s s s s s s s s State Q2 Q1 Q0 Q2.D Q1.D Q0.D

3-Bit Down Counter Q2 Q1 Q Q0.D Q0.D = ! Q0 s s s s s s s s State Q2 Q1 Q0 Q2.D Q1.D Q0.D

If load = 1, Load D to [Q2..0] MODULE dncnt3ld TITLE '3-bit Down Counter with Clear and Load' DECLARATIONS hex7seg interface([D3..D0] -> [a,b,c,d,e,f,g]); d7R FUNCTIONAL_BLOCK hex7seg; " INPUT PINS " CLK PIN 12; " 1 Hz clock (jumper) clear PIN 11;" switch S6:1 load PIN 7;" switch S6:2 D2..D0 PIN 4,3,2 ISTYPE 'com'; " switch S7:1-3 D = [D2..D0];" 3-bit input " OUTPUT PINS " Q2..Q0 PIN 41,43,44 ISTYPE 'reg'; " LED Q = [Q2..Q0]; " 3-bit output vector LED9, LED10 PIN 35,36 ISTYPE 'com'; " LED 9,10 timeout PIN 37ISTYPE 'com';" LED 11 [a,b,c,d,e,f,g] PIN 15,18,23,21,19,14,17 ISTYPE 'com'; " Rightmost (units) 7-segment LED display dncnt3ld.abl timeout = 1 when [Q2..0] = [0,0,0]

EQUATIONS LED9 = clear; LED10 = load; Q.C = CLK; Q.AR = clear; WHEN load THEN Q.D = D; ELSE { Q2.D = !Q2 & !Q1 & !Q0 # Q2 & Q1 # Q2 & Q0; Q1.D = !Q1 & !Q0 # Q1 & Q0; Q0.D = !Q0; } timeout = !Q0 & !Q1 & !Q2; [a,b,c,d,e,f,g] = d7R.[a,b,c,d,e,f,g]; d7R.[D2..D0] = Q; d7R.D3 = 0; dncnt3ld.abl (cont’d) If load = 1, Load D to [Q2..0] timeout = 1 when [Q2..0] = [0,0,0] Down counter equations

test_vectors([CLK, clear, load, D] -> [Q, timeout]) [.c.,1,0,0] -> [0,1]; [.c.,0,0,0] -> [7,0]; [.c.,0,0,0] -> [6,0]; [.c.,0,0,0] -> [5,0]; [.c.,0,0,0] -> [4,0]; [.c.,0,0,0] -> [3,0]; [.c.,0,1,5] -> [5,0]; [.c.,0,0,0] -> [4,0]; [.c.,0,0,0] -> [3,0]; [.c.,0,0,0] -> [2,0]; [.c.,0,0,0] -> [1,0]; [.c.,0,0,0] -> [0,1]; [.c.,0,0,0] -> [7,0]; END dncnt3ld.abl (cont’d)

dncnt3ld Simulation

Counters Modulo-5 Counter 3-Bit Down Counter with Load and Timeout Modulo-N Down Counter

3-Bit Down Counter with Load and Timeout To make a modulo-N counter, load I2..I0 with N-1 when timeout = 1

EQUATIONS LED9 = clear; LED10 = load; Q.C = CLK; Q.AR = clear; WHEN (load # timeout) THEN Q.D = D; ELSE { Q2.D = !Q2 & !Q1 & !Q0 # Q2 & Q1 # Q2 & Q0; Q1.D = !Q1 & !Q0 # Q1 & Q0; Q0.D = !Q0; } timeout = !Q0 & !Q1 & !Q2; [a,b,c,d,e,f,g] = d7R.[a,b,c,d,e,f,g]; d7R.[D2..D0] = Q; d7R.D3 = 0; modndcnt.abl (modified dncnt3ld.abl) If timeout = 1, Load D to [Q2..0] timeout = 1 when [Q2..0] = [0,0,0] Down counter equations

Modulo-5 Counter [D2..D0] = [1,0,0]