1. Multiplexers
Lecture L6.4
Section 6.4

2. Multiplexers A Digital Switch A 2-to-1 MUX A 4-to-1 MUX
A Quad 2-to-1 MUX
The ABEL when…then Statement
TTL Multiplexer

3. Multiplexers s1 s0 C0 C1 4 x 1 MUX Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2

4. Multiplexers 4 x 1 MUX s1 s0 C0 C1 Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2
A multiplexer is a
digital switch
0 0

5. Multiplexers 4 x 1 MUX s1 s0 C0 C1 Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2
0 1

6. Multiplexers 4 x 1 MUX s1 s0 C0 C1 Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2
1 0

7. Multiplexers 4 x 1 MUX s1 s0 C0 C1 Y C2 C3 s1 s0 0 0 C0 0 1 C1 1 0 C2
1 1

8. A 2 x 1 MUX
Z = A & !s0 # B & s0

9. A 4 x 1 MUX A = !s0 & C0 # s0 & C1 B = !s0 & C2 # s0 & C3
Z = !s1 & A # s1 & B
Z = !s1 & (!s0 & C0 # s0 & C1)
# s1 & (!s0 & C2 # s0 & C3)

10. A 4 x 1 MUX Z = !s1 & (!s0 & C0 # s0 & C1) # s1 & (!s0 & C2 # s0 & C3)

11. Problem How would you make a Quad 2-to-1 MUX?S
0 A
1 B
Quad
2-to-1
MUX
[A3..A0]
[Y3..Y0]
[B3..B0] S

12. mux.abl [A3..0] [Y3..0] [B3..0] S Quad 2-to-1 MUX MODULE Mux
TITLE 'Quad 2 to 1 Multiplexer, A. Student, 6/21/02'
DECLARATIONS
" INPUT PINS “
" OUTPUT PINS “
EQUATIONS
END Mux
Quad
2-to-1
MUX
[A3..0]
[Y3..0]
[B3..0] S

13. mux.abl Switch S6(1..4) A input vector (4 bits) Switch S7(1..4)
MODULE Mux
TITLE 'Quad 2 to 1 Multiplexer'
DECLARATIONS
" INPUT PINS "
A3..A0 PIN 11,7,6,5;
A = [A3..A0];
B3..B0 PIN 4,3,2,1;
B = [B3..B0];
S PIN 10;
Switch S6(1..4)
A input vector (4 bits)
Switch S7(1..4)
B input vector (4 bits)
Push Button
Select Line

14. mux.abl (cont’d) Defines output Output LEDs 9 – 12
" OUTPUT PINS "
Y3..Y0 PIN 35,36,37,39 ISTYPE 'com';
Y = [Y3..Y0];
EQUATIONS
Y = A & !S # B & S;
END Mux
Output LEDs 9 – 12
Output Vector Y (4 bits)
Logic Equation for the
Multiplexer

15. Mux Using Behavioral ABEL
Z = !s2 & !s1 & !s0 & C0
# !s2 & !s1 & s0 & C1
# !s2 & s1 & !s0 & C2
# !s2 & s1 & s0 & C3
# s2 & !s1 & !s0 & C0
# s2 & !s1 & s0 & C1
# s2 & s1 & !s0 & C2
# s2 & s1 & s0 & C3

16. mux81.abl MODULE mux81 TITLE '8 to 1 Multiplexer' DECLARATIONS
MODULE mux81
TITLE '8 to 1 Multiplexer'
DECLARATIONS
" INPUT PINS "
C7..C0 PIN 11,7,6,5,4,3,2,1;
C = [C7..C0];
s2..s0 PIN 70,71,72;
S = [s2..s0];
" OUTPUT PINS "
Z PIN 35 ISTYPE 'com';
EQUATIONS
when (S == 0) then Z = C0;
when (S == 1) then Z = C1;
when (S == 2) then Z = C2;
when (S == 3) then Z = C3;
when (S == 4) then Z = C4;
when (S == 5) then Z = C5;
when (S == 6) then Z = C6;
when (S == 7) then Z = C7;
@radix 16;
test_vectors ([C,S] -> Z)
[6,0] -> 0;
[7,1] -> 1;
[9,2] -> 0;
[15,3] -> 0;
[36,4] -> 1;
[47,5] -> 0;
[29,6] -> 0;
[0A5,7] -> 1;
END
mux81.abl

17. MODULE mux81
TITLE '8 to 1 Multiplexer'
DECLARATIONS
" INPUT PINS "
C7..C0 PIN 11,7,6,5,4,3,2,1;
C = [C7..C0];
s2..s0 PIN 70,71,72;
S = [s2..s0];
" OUTPUT PINS "
Z PIN 35 ISTYPE 'com';

18. EQUATIONS
when (S == 0) then Z = C0;
when (S == 1) then Z = C1;
when (S == 2) then Z = C2;
when (S == 3) then Z = C3;
when (S == 4) then Z = C4;
when (S == 5) then Z = C5;
when (S == 6) then Z = C6;
when (S == 7) then Z = C7;

19. @radix 16;
test_vectors ([C,S] -> Z)
[6,0] -> 0;
[7,1] -> 1;
[9,2] -> 0;
[15,3] -> 0;
[36,4] -> 1;
[47,5] -> 0;
[29,6] -> 0;
[0A5,7] -> 1;
END

20. Blif Simulation Report
8 to 1 Multiplexer
C C C C C C C C s s s Z
V L
V H
V L
V L
V H
V L
V L
V H
8 out of 8 vectors passed.

21. TTL Multiplexer B A C0 C1 C2 C3 G Y X X X X X X 1 0 0 0 0 X X X 0 04 5 6 7 8 9 10 11 12 13 14 15 16
GND
Vcc 1G B
1C3
1C2
1C1
1C0 1Y 2G A
2C3
2C2
2C1
2C0 2Y
74LS153
X X X X X X 1 0
X X X 0 0
X X X 0 1
0 1 X 0 X X 0 0
0 1 X 1 X X 0 1
1 0 X X 0 X 0 0
1 0 X X 1 X 0 1
1 1 X X X
1 1 X X X
Dual 4-to-1-line multiplexer