courseware High-Level Synthesis an introduction Prof. Jan Madsen Informatics and Mathematical Modelling Technical University of Denmark Richard Petersens Plads, Building 321 DK2800 Lyngby, Denmark

SoC-MOBINET coursewareM-1 High-Level Synthesis2 Hardware synthesis P1P1 P2P2 P3P3 CPU ASIC P1P1 P 2 & P 3  Starts from an abstract behavioral description  Generates an RTL description  Need to restrict the target hardware – otherwise search space is too large

SoC-MOBINET coursewareM-1 High-Level Synthesis3 Hardware synthesis P1P1 P2P2 P3P3 CPU ASIC P1P1 P 2 & P 3  How is the behavior specified?  Natural languages  C/C++  VHDL/Verilog  What is the target architecture of the ASIC?

SoC-MOBINET coursewareM-1 High-Level Synthesis4 Hardware model - components  Most synthesis systems are targeted towards synchronous hardware  Functional units:  Can perform one or more computations  Addition, multiplication, comparison, ALU, etc.  Registers:  Store inputs, intermediate results and outputs  May be organized as a register file

SoC-MOBINET coursewareM-1 High-Level Synthesis5 Hardware model - interconnection  Multiplexers:  Select one output from several inputs  Busses:  Connection shared between several components  Only one component can write data at a specific time  Exclusive writing may be controlled by tri-state drivers

SoC-MOBINET coursewareM-1 High-Level Synthesis6 Hardware model – parameters  Clocking strategy  Single or multiple phase clocks  Interconnect  Allowing or disallowing busses  Clocking of functional units  Multicycle operations  Chaining  Pipelined units

SoC-MOBINET coursewareM-1 High-Level Synthesis7 Hardware model – example

SoC-MOBINET coursewareM-1 High-Level Synthesis8 Hardware concepts  Data path  Network of functional units, registers, multiplexers and buses  Control  Takes care of having the data present at the right place at a specific time  Takes care of presenting the right instructions to a programmable unit  Often high-level synthsis concentrates on data path synthesis

SoC-MOBINET coursewareM-1 High-Level Synthesis9 Methodology implementation design specification Physical domain Mathematical domain specification create a model of the physical problem synthesis create an alogorithm to solve the problem implementation Transform the optimized model back to the physical domain

SoC-MOBINET coursewareM-1 High-Level Synthesis10 Input format  Input  Behavior described in textual form  Conventional programming language  Hardware description language (HDL)  Has to be parsed and transformed into an internal representation  Conventional compiler techniques are used

SoC-MOBINET coursewareM-1 High-Level Synthesis11 Internal representation  Data-flow graph (DFG)  Used by most systems  May or may not contain information on control flow vertex (node): represent computation edge: represent precedence relations

SoC-MOBINET coursewareM-1 High-Level Synthesis12 Data flow x := a * b; y := c + d; z := x + y; abcd x * y + z +

SoC-MOBINET coursewareM-1 High-Level Synthesis13 DFG semantics abcd x * y + z +

SoC-MOBINET coursewareM-1 High-Level Synthesis14 Exercise 1: data flow graph of DiffEq  Solve the second order differential equation  y´´ + 3zy´+ 3y = 0  Iterative solution While (z<a) { z1 := z + dz; u1 := u – (3*z*u*dz) – (3*y*dz); y1 := y + (u*dz); z := z1; u := u1; y := y1; }

SoC-MOBINET coursewareM-1 High-Level Synthesis15 Exercise 1 - result + u1 -*-*****+< udz 3 z 3 yu z y1ctrl

SoC-MOBINET coursewareM-1 High-Level Synthesis16 High-level synthesis abcd xy + z + *

SoC-MOBINET coursewareM-1 High-Level Synthesis17 High-level synthesis  Scheduling  Determine for each operation the time at which it should be performed such that no precedence contraint is violated  Allocation  Specify the hardware resources that will be necessary  Assignment  Provide a mapping from each operation to a specific functional unit and from each variable to a register

SoC-MOBINET coursewareM-1 High-Level Synthesis18 High-level synthesis  Scheduling, allocation and assignment are strongly interrelated  But are often solved separately!  Scheduling is NP-complete – heuristics have to be used!

SoC-MOBINET coursewareM-1 High-Level Synthesis19 Scheduling  Input  DFG G(V, E)  Library of ressource types R  Mapping   : V  R,  (v i ) = r  a given operation may be mapped to different ressource type, e.g. + may be performed by an adder or an ALU  execution delay:  (v i ) = d i  ressource type cost:  (r)

SoC-MOBINET coursewareM-1 High-Level Synthesis20 Scheduling  Start time of operations  T = { t i : i = 0, 1, …, n }  Scheduling is the task of determining the start times subject to the precedence constraints of the DFG   : V  Z +   v i ) = t i such that t i  t j + d j,  i, j : (v j, v i )  E  Latency: = t n – t 0  Cost of schedule:  r  R  (r) N r (  )]

SoC-MOBINET coursewareM-1 High-Level Synthesis21 Scheduling implementation specification Physical domain Mathematical domain specification synthesis implementation C program DFG Scheduling algorithm Scheduled DFG

SoC-MOBINET coursewareM-1 High-Level Synthesis22 Scheduling – ASAP  Map operations to their earliest possible start time not violating the precedence constraints  Easy and fast to compute  Find longest path in a directed acyclic graph  No attemp to optimize ressource cost  Gives the fastest possible schedule if unlimited amount of resources are available  Gives an upper bound on execution speed

SoC-MOBINET coursewareM-1 High-Level Synthesis23 ASAP algorithm For each node v i  V do if pred(v i ) = Ø then E i = 1; V = V – { v i }; else E i = 0; endif endfor While V ≠ Ø do for each node v i  V do if all_sched(pred(v i ),E) then E i = max(pred(v i ),E) + 1; V = V – { v i }; endif endfor endwhile

SoC-MOBINET coursewareM-1 High-Level Synthesis24 DiffEq + u1 -*-*****+< udz 3 z 3 yz y1ctrl udz

SoC-MOBINET coursewareM-1 High-Level Synthesis25 Exercise 2 – latency and resources  Assume:  cycle time = 25 ns  d *, d +, d -, d < = 25 ns  What is the latency of the schedule?  How many resources are needed?  How many resources are needed, if we introduce an ALU (+,-,<)  What is the latency if we have only 1 multiplier?  What is the latency if  d * = 25ns and d ALU = 12ns

SoC-MOBINET coursewareM-1 High-Level Synthesis26 Exercise 2 – result  What is the latency of the schedule?  4*25ns = 100ns  How many resources are needed?  4*, 1+, 1-, 1<  How many resources are needed, if we introduce an ALU (+,-,<)  4*, 2ALU  What is the latency if we have only 1 multiplier?  7*25ns = 175ns  What is the latency if  d * = 25ns and d ALU = 12ns  3*25ns = 75ns (operator chaining)

SoC-MOBINET coursewareM-1 High-Level Synthesis27 Scheduling - ALAP + u1 - * - * ** * * +< udz 3 z 3 yz y1ctrl udz

SoC-MOBINET coursewareM-1 High-Level Synthesis28 Scheduling – ALAP  Map operations to their latest possible start time not violating the precedence constraints  Needs a latency constraint  Easy and fast to compute  Find longest path in a directed acyclic graph  No attemp to optimize ressource cost

SoC-MOBINET coursewareM-1 High-Level Synthesis29 Scheduling – ASAP / ALAP  Are ASAP and ALAP useful?   ASAP  v i ) = E i   ALAP  v i ) = L i  Operator flexibility = L i – E i  Also known as mobility  Mobility = 0  operator has to be scheduled at E i  otherwise latency constraint is violated  Mobility > 0 gives scheduling freedom

SoC-MOBINET coursewareM-1 High-Level Synthesis30 Scheduling – list based  Generalization of ASAP  Priority-list of ready nodes  A ready node is an operator that has all predecessors already scheduled  The priority-list is always sorted with respect to a priority function

SoC-MOBINET coursewareM-1 High-Level Synthesis31 List scheduling algorithm ins_ready_ops(V,PList r 1, PList r 2,…, PList r m ); Cstep = 0; While ((PList r 1  Ø) or … or ((PList r m  Ø)) do Cstep = Cstep + 1; for k = 1 to m do for funit = 1 to N k do if PList r k  Ø then schdule_op(first(Plist r k ),Cstep); Plist r k = delete(Plist r k,first(Plist r k )); endif endfor ins_ready_ops(V,PList r 1, PList r 2,…, PList r m ); endwhile

SoC-MOBINET coursewareM-1 High-Level Synthesis32 DiffEq + u1 -*-*****+< udz 3 z 3 yz y1ctrl udz [h,0] [g,0] [a,0][b,0] [e,0][f,1] [c,1][d,2] [i,2] [k,2] [j,2] Plist * : Plist + : Plist - : Plist < : a,b,c,d j Ø Ø ** + -< ** c,d e,c,d * Ø k * * * Ø f,d g

SoC-MOBINET coursewareM-1 High-Level Synthesis33 List scheduling  Priority may be based on other measures than mobility  Length of longest path to a node with no immediate successor  Number of immediate successor nodes  High number means high priority