1. VLSI DSP 2008Y.T. Hwang3-1 Chapter 3 Algorithm Representation & Iteration Bound

2. VLSI DSP 2008Y.T. Hwang3-2 Representations of DSP Algorithms Mathematical formulations Behavioral description languages Applicative language  Represents a set of equations satisfied by the variables, e.g. Silage Perspective language  Explicitly specify the order of assignment, e.g. C and other HLLs Descriptive language  Represents the structure of a DSP system, e.g. VHDL, Verilog Graphical representations Block diagrams Signal flow graph (SFG) Data flow graph (DFG) Dependence graph (DG)

3. VLSI DSP 2008Y.T. Hwang3-3 Block Diagrams (1) Consists of functional blocks connected with directed edges Functional block, e.g. Add, Mult Unit delay element Directed edge representing the data flow between blocks Basic blocks

4. VLSI DSP 2008Y.T. Hwang3-4 Block Diagrams (2) 3-tap FIR example Alternative block diagram with data broadcast

5. VLSI DSP 2008Y.T. Hwang3-5 Signal Flow Graph (1) A collection of nodes and directed edges Node: computation or task Directed edge (j,k)  a linear transformation from node j to node k  Usually as constant gain multiplier or delay elements Widely used in digital filter structures Flow graph reversal (transposition) A transform to obtain equivalent structure Applicable to single-input single output system Reverse the directions of all edges Exchange the input output node Retain the edge gain and edge delay

6. VLSI DSP 2008Y.T. Hwang3-6 Signal Flow Graph (2) SFG of a 3-tap FIR filter Original SFG Transposed SFG

7. VLSI DSP 2008Y.T. Hwang3-7 Signal Flow Graph (3) Limitations of transposition can be applied to MIMO systems described by symmetric transform matrices More on SFG Applicable to linear network Cannot be used to described multi-rate system

8. VLSI DSP 2008Y.T. Hwang3-8 Data Flow Graph (1) DFG Node: computation (function or subtask) Directed edge: data path or communication between nodes Associated edge delay: non-negative Associated node delay: execution time of each node Block diagram Conventional DFG Synchronous DFG add mpy

9. VLSI DSP 2008Y.T. Hwang3-9 Data Flow Graph (2) Applications: high level synthesis Firing rules A node can fire whenever all the input data are available Concurrency: multiple nodes can be fired simultaneously Data driven (implicit) scheduling Precedence constraint Intra-iteration: imposed by edge with no delay Inter-iteration: imposed by edge with delay fine-grain (atomic) v.s. coarse grain DFG

10. VLSI DSP 2008Y.T. Hwang3-10 Data Flow Graph (3) 3-tap FIR filter example Direct form Transpose form

11. VLSI DSP 2008Y.T. Hwang3-11 Data Flow Graph (4) Synchronous DFG Number of data samples produced or consumed by each node is specified a priori Single rate system Multi-rate system: different nodes working on different frequencies Multi-rate system can be represented by a single rate system via unfolding (unrolling)

12. VLSI DSP 2008Y.T. Hwang4-12 Introduction to Iteration bound DSP algorithms often contain feedback loops Impose an inherent lower bound on the achievable iteration or sample period Iteration bound Impossible to achieve an iteration period less than the iteration bound even with infinite HW Iteration k Iteration k-1 Iteration k+1 Iteration k+2 t Iteration period

13. VLSI DSP 2008Y.T. Hwang4-13 Data Flow Graph Representations For n = 0 to ∞ y(n) = ay(n-1) + x(n) Iteration – execution of each DFG node once Precedence constraints Intra-iteration – no delay on edge Inter-iteration – at least one delay on edge Execution time of a node Inter- iteration Intra- iteration Critical path A  B

14. VLSI DSP 2008Y.T. Hwang4-14 Critical Path Critical path of a DFG The path with the longest computation time among all paths containing zero delays The minimum computation time for one iteration of the DFG 6 → 3→2→1 5 → 3→2→1 Iteration period = 5 u.t. Iteration bound Recursive DFG has a lower bound on the shortest iteration period

15. VLSI DSP 2008Y.T. Hwang4-15 Loop bound and iteration bound (1) Loop bound Minimum time to execute one loop in the DFG t l / w l : t l = loop computation time, w l = number of delays in the loop (a) loop bound = (4+2)/2 = 3 (b) loop bound 1 = (4+2)/2 = 3 (b) loop bound 2 = (2+4+5)/1 = 11

16. VLSI DSP 2008Y.T. Hwang4-16 Loop bound and iteration bound (2) In (a), two independent sets of computing threads Two iterations in every 6 u.t.  iteration period = 3 u.t. A 0 →B 0  A 2 →B 2  A 4 →B 4  A 6 →… A 1 →B 1  A 3 →B 3  A 5 →B 5  A 7 →… In (b) Loop 1: A→B→A Loop 2: A→B→C→A (critical loop)

17. VLSI DSP 2008Y.T. Hwang4-17 Loop bound and iteration bound (3) Loop bound of the critical loop  iteration bound of the DSP algorithm Algorithms to find T ∞ Longest path matrix algorithm Minimum cycle mean algorithm Negative cycle detection algorithm